# US 9,520,379 B2 · Method of forming bump structure having a side recess and semiconductor structure including the same

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- Number: US 9,520,379 B2
- Document ID: US9520379B2
- Status: Granted
- Kind: B2
- Application number: 15/057,302
- Filed: 2016-03-01
- Published: 2016-06-23
- Granted: 2016-12-13
- Earliest claimed: 2011-07-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Horng Chang; Tin-Hao Kuo; Chen-Shien Chen; Yen-Liang Lin
- Web page: https://patentgrep.com/patent/US9520379B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/01257: {by reflowing}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/231: {Shapes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/287: {Flow barriers}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/951: {Materials of bond pads}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 428/12493: Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T 428/24479: including variation in thickness
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work piece, and a conductive bump on a surface of a second work piece. The conductive bump has a recess. A reflow process is performed on a solder layer to electrically couple the conductive trace and the conductive bump. The solder layer fills a part of the recess during the reflow process. By filling the recess during the reflow process, electrical shorting between the conductive trace and an adjacent conductive is reduced.

## Claims

### Claim 1

A method of integrated chip bonding, comprising:
forming a conductive trace on a surface of a first work piece;
forming a conductive bump on a surface of a second work piece, wherein the conductive bump has a recess;
forming a second conductive trace on the surface of the first work piece; and
performing a reflow process on a solder layer to electrically couple the conductive trace and the conductive bump, wherein the solder layer fills a part of the recess during the reflow process and wherein the recess faces the second conductive trace.

### Claim 2 (depends on 1)

The method of claim 1, wherein the recess extends into the conductive bump to a depth having a range of between approximately 0.5 um and approximately 15 um.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming a second conductive bump having a second recess, wherein the recess of the conductive bump is oriented in a first direction and the second recess of the second conductive bump is oriented in a second direction different from the first direction.

### Claim 4 (depends on 1)

The method of claim 1, wherein the conductive bump comprises:
a first end;
a second end opposite the first end;
a first side connected between the first end and the second end; and
a second side opposite the first side, wherein the second side is connected between the first end and the second end, and the second side comprises the recess.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first side is a non-recessed side.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming the conductive bump onto an under-bump metallurgy (UBM) layer of the first work piece.

### Claim 7 (depends on 6)

The method of claim 6, wherein the recess is arranged within sidewalls of the solder layer, the conductive bump, and the UBM layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the conductive bump comprises a
copper pillar.

### Claim 9 (depends on 1)

The method of claim 1, wherein the solder layer contacts sidewalls of metal trace after performing the reflow process.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
forming a mold underfill (MUF) vertically between the first work piece and the second work piece after bonding the first work piece to the second work piece, wherein the MUF laterally surrounds the conductive trace.

### Claim 11

A method of integrated chip bonding, comprising:
forming a conductive trace on a surface of a first work piece;
forming a conductive bump on a surface of a second work piece, wherein the conductive bump has a first end, a second end opposite the first end, and a first side connected between the first end and the second end, wherein the first side comprises a recess; and
electrically coupling the conductive trace and the conductive bump by heating the first work piece or the second work piece.

### Claim 12 (depends on 11)

The method of claim 11, wherein the conductive bump further comprises a second side opposite the first side, and wherein the second side is a non-recessed side.

### Claim 13 (depends on 11)

The method of claim 11, wherein the conductive bump has a greater width than the conductive trace.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
forming a second conductive trace on the surface of a first work piece, wherein the recess faces the second conductive trace.

### Claim 15 (depends on 11)

The method of claim 11, wherein electrically coupling the conductive trace and the conductive bump comprises performing a reflow process on a solder layer to electrically couple the conductive trace and the conductive bump, wherein the solder layer contacts sidewalls of metal trace after solder reflow.

### Claim 16

A method of integrated chip bonding, comprising:
forming a metal trace on a surface of a first work piece, wherein the metal trace has a first width;
forming a conductive bump having a recess onto a surface of a second work piece, wherein the conductive bump has a top surface facing away from the second work piece and a bottom surface facing the second work piece, and wherein the top surface has a second width that is larger than the first width and the bottom surface has a third width that is smaller than the second width; and
forming a solder layer between the metal trace and the conductive bump, wherein the solder layer fills a part of the recess.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the solder layer comprises performing a reflow process on the solder layer to electrically couple the metal trace and the conductive bump, wherein the reflow process causes the solder layer to fill a part of the recess and to contact sidewalls of the metal trace and the conductive bump.

### Claim 18 (depends on 17)

The method of claim 17, wherein the solder layer has an outer surface facing away from the metal trace that curves between the metal trace and the conductive bump after the reflow process.

### Claim 19 (depends on 16)

The method of claim 16, wherein the conductive bump comprises:
a first end;
a second end opposite the first end; and
a side connected between the first end and the second end, wherein the side comprises the recess.

### Claim 20 (depends on 16)

The method of claim 16, wherein the recess extends into the conductive bump to a depth having a range of between approximately 0.5 um and approximately 15 um.