# US 9,520,377 B2 · Semiconductor device package including bonding layer having Ag3Sn > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,377 B2 - Document ID: US9520377B2 - Status: Granted - Kind: B2 - Application number: 14/311,708 - Filed: 2014-06-23 - Published: 2015-04-30 - Granted: 2016-12-13 - Earliest claimed: 2013-10-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jeong-Won Yoon; Baik-woo Lee; Seong-woon Booh; Chang-mo Jeong - Web page: https://patentgrep.com/patent/US9520377B2 ## CPC - B23K 1/0016: {Soldering of electronic components} - B23K 20/023: {Thermo-compression bonding} - B23K 20/16: with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas - B23K 20/233: without ferrous layer - B23K 35/0244: {Powders, particles or spheres; Preforms made therefrom} - B23K 35/025: {Pastes, creams or slurries} - H10W 72/0198: {batch processes} - B23K 2101/42: Printed circuits - H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/073: {of die-attach connectors} - H10W 72/07331: {Connecting techniques} - H10W 72/07332: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07336: {Soldering or alloying} - H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature} - H10W 72/07354: {changes in dispositions} - H10W 72/07355: {changes in materials} - H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/351: {Materials of die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/3528: {Intermetallic compounds} - H10W 72/381: {Auxiliary members} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag3Sn. A method of manufacturing the semiconductor device package may include forming a bonding layer, which bonds a semiconductor chip to a substrate, by using a mixed paste including metal particles and a solder material. The bonding layer may be formed by forming an intermetallic compound, which is formed by heating the mixed paste to react the metal particles with the solder material. ## Claims ### Claim 1 A semiconductor device package comprising: a first substrate; at least one semiconductor chip mounted on the first substrate; a first bonding layer provided between the first substrate and the semiconductor chip, the first bonding layer including Ag3Sn grains; and a metal layer provided between the first bonding layer and the semiconductor chip, the metal layer including a non-solder material, the first bonding layer in contact with the metal layer and the first substrate, wherein the first bonding layer is substantially devoid of pores, wherein the Ag3Sn grains are substantially uniformly distributed throughout the first bonding layer, and the Ag3Sn grains are in contact with the first substrate, and wherein the first bonding layer includes Ag material and the Ag3Sn gains, and the Ag material exists between the Ag3Sn grains. ### Claim 2 (depends on 1) The semiconductor device package of claim 1, wherein a content of the Ag3Sn grains in the first bonding layer is equal to or greater than about 90 wt %. ### Claim 3 (depends on 1) The semiconductor device package of claim 1, wherein the first bonding layer includes a mixture of the Ag material and the Ag3Sn grains. ### Claim 4 (depends on 1) The semiconductor device package of claim 1, wherein the first bonding layer includes a mixture of the Ag material, the Ag3Sn grains, and a solder material. ### Claim 5 (depends on 4) The semiconductor device package of claim 4, wherein a content of the solder material in the mixture is equal to or less than about 10 wt %. ### Claim 6 (depends on 1) The semiconductor device package of claim 1, wherein a content of the Ag3Sn grains in the first bonding layer is equal to or greater than about 50 wt %. ### Claim 7 (depends on 1) The semiconductor device package of claim 1, wherein the metal layer includes at least one of Al, Cu, Ni, Ag, Au, or an alloy thereof. ### Claim 8 (depends on 1) The semiconductor device package of claim 1, wherein the first substrate is one selected from among a direct bonded copper (DBC) substrate, a direct bonded aluminum (DBA) substrate, a printed circuit board (PCB), and a lead frame. ### Claim 9 (depends on 1) The semiconductor device package of claim 1, further comprising: a plurality of semiconductor chips including the at least one semiconductor chip. ### Claim 10 (depends on 1) The semiconductor device package of claim 1, further comprising: a base plate attached to the first substrate; and a second bonding layer provided between the base plate and the first substrate, the second bonding layer having a same configuration as the first bonding layer. ### Claim 11 (depends on 1) The semiconductor device package of claim 1, wherein the first substrate is attached to a first surface of the semiconductor chip, and the semiconductor device package further comprises, a second substrate attached to a second surface of the semiconductor chip, the second surface opposite to the first surface, and a second bonding layer provided between the second substrate and the semiconductor chip, the second bonding layer having a same configuration as the first bonding layer. ### Claim 12 (depends on 11) The semiconductor device package of claim 11, further comprising: at least one of a first base plate attached to the first substrate and a second base plate attached to the second substrate. ### Claim 13 (depends on 1) The semiconductor device package of claim 1, wherein the at least one semiconductor chip includes at least one power device. ### Claim 14 (depends on 1) The semiconductor device package of claim 1, wherein the first bonding layer further includes a solder material, and wherein a content of the solder material in the first bonding layer is equal to or less than 5 wt %. ### Claim 15 (depends on 1) The semiconductor device package of claim 1, wherein the first bonding layer covers an entirety of a facing surface of the semiconductor chip. ### Claim 16 (depends on 1) The semiconductor device package of claim 1, wherein a sum of contents of the Ag3Sn grains and the Ag material in the first bonding layer is equal to or greater than about 90 wt %. ### Claim 17 (depends on 1) The semiconductor device package of claim 1, wherein a content of Ag in the first bonding layer is at least three times a content of Sn in the first bonding layer.