# US 9,520,376 B2 · Bumpless build-up layer package including an integrated heat spreader

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,376 B2
- Document ID: US9520376B2
- Status: Granted
- Kind: B2
- Application number: 14/875,247
- Filed: 2015-10-05
- Published: 2016-01-28
- Granted: 2016-12-13
- Earliest claimed: 2012-09-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Weng Hong Teh; Deepak Kulkarni; Chia-Pin Chiu; Tannaz Harirchian; John S. Guzek
- Web page: https://patentgrep.com/patent/US9520376B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 40/10: Arrangements for heating
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 40/778: {in encapsulations}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/01: Manufacture or treatment
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/722: {between stacked chips}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

## Claims

### Claim 1

A microelectronic die assembly, comprising:
a microelectronic die coupled to a plurality of build-up layers on a first side of the microelectronic die;
a heat spreader thermally coupled to a second side of the microelectronic die, opposite the first side;
an encapsulation material covering the microelectronic die and at least a portion of the heat spreader; and
a grid of thermal conductors disposed between the plurality of build-up layers and the first side of the microelectronic die, the grid interlaced around a plurality of electrical contacts between die and the plurality of build-up layers.

### Claim 2 (depends on 1)

The microelectronic die assembly of claim 1, wherein the grid of thermal conductors is thermally coupled to the heat spreader.

### Claim 3 (depends on 2)

The microelectronic die assembly of claim 2, wherein the grid of thermal conductors is thermally coupled to the heat spreader using one or more plated and filled vias.

### Claim 4 (depends on 1)

The microelectronic die assembly of claim 1, further including a second microelectronic die coupled between the heat spreader and the plurality of build-up layers.

### Claim 5 (depends on 4)

The microelectronic die assembly of claim 4, further including a second grid of thermal conductors disposed between the microelectronic die and the second microelectronic die.

### Claim 6 (depends on 5)

The microelectronic die assembly of claim 5, wherein the second grid of thermal conductors is thermally coupled to the heat spreader.

### Claim 7 (depends on 6)

The microelectronic die assembly of claim 6, wherein the second grid of thermal conductors is thermally coupled to the heat spreader using one or more plated and filled vias.