# US 9,520,374 B2 · Semiconductor device, substrate and semiconductor device manufacturing method

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- Number: US 9,520,374 B2
- Document ID: US9520374B2
- Status: Granted
- Kind: B2
- Application number: 14/322,461
- Filed: 2014-07-02
- Published: 2014-10-23
- Granted: 2016-12-13
- Earliest claimed: 2005-06-06
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Yasumasa Kasuya; Motoharu Haga; Hiroaki Matsubara
- Web page: https://patentgrep.com/patent/US9520374B2

## CPC

- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01308: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane.

## Claims

### Claim 1

A semiconductor device including a BGA (Ball Grid Array) configuration, comprising:
a semiconductor chip;
a conductive layer disposed at a back surface of the semiconductor chip;
an interposer disposed on a lower side of the conductive layer to support the semiconductor chip;
an internal terminal formed on the interposer;
a sealing resin to seal the semiconductor chip and a surface of the interposer that is adjacent to the semiconductor chip; and
a plurality of external terminals formed in a ball shape on an opposite surface of the interposer from a surface of the interposer on which the conductive layer is provided,
wherein the conductive layer includes:
a first portion disposed such that an outer periphery thereof is inside an outer periphery of the semiconductor chip as seen from above; and
a second portion extending outward from a part of the outer periphery of the first portion, wherein an end part thereof extends toward a corner of the semiconductor chip as seen from above,
wherein each of a plurality of sides of the semiconductor chip has an edge line corresponding to the opposing edge line of the first portion,
wherein a surface of the second portion of the conductive layer and a surface of the internal terminal are in the same plane,
wherein the second portion of the conductive layer is disposed in the sealing resin and the end part thereof is covered by the sealing resin,
wherein the end part of the second portion is disposed adjacent to the corner of the semiconductor chip as viewed from above, and
wherein the plurality of external terminals are disposed in a grid-like arrangement.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a bonding wire connecting a front surface of the semiconductor chip and the internal terminal.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising at least one additional internal terminal, the internal terminals being spaced apart from each other and surrounding the conductive layer as seen from above.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a bonding layer interposed between the back surface of the semiconductor chip and the conductive layer.

### Claim 5

A semiconductor device including a BGA (Ball Grid Array) configuration, comprising:
a semiconductor chip;
a conductive layer disposed at a back surface of the semiconductor chip;
an interposer disposed on a lower side of the conductive layer to support the semiconductor chip;
an internal terminal formed on the interposer;
a sealing resin to seal the semiconductor chip and a surface portion of the interposer; and
a plurality of external terminals formed in a ball shape on an opposite surface of the interposer from a surface of the interposer on which the conductive layer is provided,
wherein the conductive layer includes:
a first portion disposed such that an outer periphery thereof is inside an outer periphery of the semiconductor chip as seen from above; and
a second portion extending outward from a part of the outer periphery of the first portion, wherein an end part thereof extends toward a corner of the semiconductor chip as seen from above,
wherein at least one of a plurality of sides of the semiconductor chip has an edge that faces a corresponding edge of the first portion of the conductive layer and is spaced apart from the corresponding edge by a substantially uniform distance,
wherein a surface of the second portion of the conductive layer and a surface of the internal terminal are in the same plane,
wherein the second portion of the conductive layer is disposed in the sealing resin and the end part thereof is covered by the sealing resin,
wherein the end part of the second portion is disposed adjacent to the corner of the semiconductor chip as viewed from above, and
wherein the plurality of external terminals are disposed in a grid-like arrangement.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, further comprising a bonding wire connecting a front surface of the semiconductor chip and the internal terminal.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, further comprising at least one additional internal terminal, the internal terminals being spaced apart from each other and surrounding the conductive layer as seen from above.

### Claim 8 (depends on 5)

The semiconductor device according to claim 5, further comprising a bonding layer interposed between the back surface of the semiconductor chip and the conductive layer.