# US 9,520,372 B1 · Wafer level package (WLP) and method for forming the same

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- Number: US 9,520,372 B1
- Document ID: US9520372B1
- Status: Granted
- Kind: B1
- Application number: 14/837,712
- Filed: 2015-08-27
- Granted: 2016-12-13
- Earliest claimed: 2015-07-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shin-Puu Jeng; Hsien-Wen Liu
- Web page: https://patentgrep.com/patent/US9520372B1

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10P 14/683: {carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/69: Insulating materials thereof
- H10W 72/01925: {in solid form}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate;
a conductive pad formed on the substrate;
a protection layer formed over the conductive pad;
a post-passivation interconnect (PPI) structure and a PPI pad formed at least in the protection layer, wherein the PPI structure is electrically connected to the conductive pad, and the PPI structure is formed on the PPI pad;
a first moisture-resistant layer formed over the protection layer, wherein the protection layer and the first moisture-resistant layer are made of different materials; and
an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the first moisture-resistant layer comprises polyimide (PI), epoxy, solder resist (SR), silicon nitride, silicon oxide, HMDS (hexamethyldisilazane), fluorine-containing polymer or combinations thereof.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the protection layer is made of polybenzoxazole (PBO), and the first moisture-resistant layer is made of polyimide (PI), wherein the polyimide (PI) comprises cross-links with a range from about 10 wt % to about 40 wt %.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a second moisture-resistant layer formed over the first moisture-resistant layer and adjacent to the UBM layer.

### Claim 5 (depends on 4)

The semiconductor device structure as claimed in claim 4, wherein the second moisture-resistant layer is made of fluorine-containing polymer, wherein the fluorine-containing polymer comprises carbon-fluorine (C—F) bonds with a range from about 30 wt % to about 60 wt %.

### Claim 6 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a conductive structure formed over the UBM layer, wherein the conductive structure is electrically connected to the PPI structure by the UBM layer.

### Claim 7 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a package structure formed over the conductive structure, wherein the conductive structure is electrically connected to a conductive pad of the package structure.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a passivation layer formed between the conductive pad and the PPI structure, wherein the passivation layer and the first moisture-resistant layer are made of the same material.

### Claim 9

A semiconductor device structure, comprising:
a conductive pad formed over a chip;
an insulating layer surrounding the chip;
a protection layer formed over the conductive pad and the insulating layer;
a post-passivation interconnect (PPI) structure at least formed in the protection layer, wherein the PPI structure is electrically connected to the conductive pad;
a first moisture-resistant layer formed over the protection layer, wherein the first moisture-resistant layer comprises polyimide (PI), epoxy, solder resist (SR), silicon nitride, silicon oxide, HMDS (hexamethyldisilazane), fluorine-containing polymer or combinations thereof; and
an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer.

### Claim 10 (depends on 9)

The semiconductor device structure as claimed in claim 9, further comprising:
a passivation layer formed between the chip and the protection layer, wherein the passivation layer and the first moisture-resistant layer are made of the same material.

### Claim 11 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein the solder resist (SR) comprises silicate fillers with a range from about 10 wt % to about 30 wt %.

### Claim 12 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein the epoxy comprises phenol resin or acrylic resin with a range from about 60 wt % to about 90 wt %.

### Claim 13 (depends on 9)

The semiconductor device structure as claimed in claim 9, further comprising:
a first conductive structure formed on the UBM layer; and
a first package structure formed over the first conductive structure.

### Claim 14 (depends on 9)

The semiconductor device structure as claimed in claim 9, further comprising:
a conductive pillar structure formed through the insulating layer, wherein the conductive pillar structure comprises a first surface which is adjacent to the PPI structure and a second surface opposite to the first surface; and
a conductive layer formed over the second surface of the conductive pillar structure.

### Claim 15 (depends on 14)

The semiconductor device structure as claimed in claim 14, further comprising:
a second conductive structure formed over the conductive layer; and
a second package structure formed over the second conductive structure.

### Claim 16 (depends on 9)

The semiconductor device structure as claimed in claim 9, further comprising:
a second moisture-resistant layer formed over the first moisture-resistant layer, wherein the second moisture-resistant layer is adjacent to the UBM layer.

### Claim 17

A method for forming a semiconductor device structure, comprising:
forming a conductive pad over a substrate;
forming a protection layer formed over the conductive pad;
forming a post-passivation interconnect (PPI) structure and a PPI pad in the protection layer, wherein the PPI structure is electrically connected to the conductive pad, and the PPI structure is formed on the PPI pad;
forming a first moisture-resistant layer over the protection layer, wherein the protection layer and the first moisture-resistant layer are made of different materials; and
forming an under bump metallurgy (UBM) layer in the first moisture-resistant layer.

### Claim 18 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
forming a second moisture-resistant layer adjacent to the UBM layer, wherein the second moisture-resistant layer is made of fluorine-containing polymer.

### Claim 19 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
forming a conductive structure over the UBM layer; and
forming a package structure over the conductive structure, wherein the package structure is electrically connected to the conductive structure.

### Claim 20 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
forming a chip structure between the conductive pad and the substrate;
forming an insulating layer surrounding the chip; and
forming a conductive pillar structure through the insulating layer and adjacent to the chip structure.