# US 9,520,371 B2 · Planar passivation for pads

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- Number: US 9,520,371 B2
- Document ID: US9520371B2
- Status: Granted
- Kind: B2
- Application number: 14/525,154
- Filed: 2014-10-27
- Published: 2016-04-28
- Granted: 2016-12-13
- Earliest claimed: 2014-10-27
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Benfu Lin; Wanbing Yi; Wei Lu; Alex See; Juan Boon Tan
- Web page: https://patentgrep.com/patent/US9520371B2

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/084: {for dual-damascene structures}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/0198: {batch processes}
- H10W 72/075: {of bond wires}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.

## Claims

### Claim 1

A device comprising:
a substrate having circuit component and a dielectric layer over the substrate, wherein the dielectric layer comprises a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer comprises at least one interconnect;
a pad dielectric layer which comprises a flowable dielectric material disposed over the uppermost ILD layer;
a pad interconnect which is a wire bond pad configured for receiving a wire bond disposed in the pad dielectric layer and a top surface of the pad interconnect is exposed such that the wire bond is to be attached and in direct contact thereto, wherein the pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer, wherein a top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect; and
a passivation layer disposed over and in direct contact with the pad dielectric layer, wherein the passivation layer comprises a non-planar top surface having a first height closer to the pad interconnect and a second height away from the pad interconnect, wherein the first height is slightly higher than the second height, and the passivation layer is used for preventing a top surface of the pad interconnect from oxidation/corrosion and contamination during wire bonding and packaging process.

### Claim 2 (depends on 1)

The device of claim 1 wherein the top surface of the pad dielectric layer is slightly below the top surface of the pad interconnect.

### Claim 3 (depends on 1)

The device of claim 1 wherein the top surface of the pad dielectric layer adjacent to the pad interconnect is slightly above the top surface of the pad interconnect.

### Claim 4 (depends on 3)

The device of claim 3 wherein the top surface of the pad dielectric layer comprises a first height and a second height away from the pad interconnect, and wherein the first height is slightly higher than the second height.

### Claim 5 (depends on 4)

The device of claim 4 wherein the passivation layer comprises a step profile.

### Claim 6

A method for forming a device comprising:
providing a substrate having circuit component and a dielectric layer over the substrate, wherein the dielectric layer comprises a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer comprises at least one interconnect;
providing a pad dielectric layer over the uppermost ILD layer, wherein providing the pad dielectric layer comprises forming a lower pad dielectric layer over the uppermost dielectric layer, and forming an upper pad dielectric layer over the lower pad dielectric layer, wherein the upper pad dielectric layer comprises a flowable dielectric material;
forming a pad interconnect which is a wire bond pad configured for receiving a wire bond in the pad dielectric layer and a top surface of the pad interconnect is exposed such that the wire bond is to be attached and in direct contact thereto, wherein the pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer, wherein a top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect; and
forming a passivation layer over and in direct contact with the pad dielectric layer, wherein the passivation layer comprises a first portion covering the pad interconnect having a first height and a second portion not covering the pad interconnect having a second height, wherein the first height is same as the second height, and
wherein the passivation layer is used for preventing a top surface of the pad interconnect from oxidation/corrosion and contamination during wire bonding and packaging process.

### Claim 7 (depends on 6)

The method of claim 6 wherein the flowable dielectric material comprises a spin on glass (SOG) layer formed by spin on process.

### Claim 8 (depends on 6)

The method of claim 6 wherein the flowable dielectric material comprises PETEOS/BPSG, polyimide or a combination thereof.

### Claim 9 (depends on 7)

The method of claim 7 wherein forming the pad interconnect comprises:
forming a pad via contact opening in the lower pad dielectric layer;
forming a conductive layer on the substrate, wherein the conductive layer fills the pad via opening and covering the lower pad dielectric layer; and
patterning the conductive layer to form the pad interconnect having a contact pad over the lower pad dielectric layer and a pad via contact in the pad via opening.

### Claim 10 (depends on 9)

The method of claim 9 wherein;
forming the pad dielectric layer comprises forming the upper pad dielectric layer covering the lower pad dielectric layer and the contact pad, wherein the upper pad dielectric layer comprises a thin portion covering the contact pad, creating a step surface profile; and comprising
patterning the passivation layer and upper pad dielectric layer to expose a top surface of the contact pad, wherein each of the passivation layer and upper dielectric layer comprises a non-planar top surface having a first height closer to the pad interconnect and a second height away from the pad interconnect, wherein the first height is slightly higher than the second height.

### Claim 11 (depends on 9)

The method of claim 9 comprising removing a portion of the upper pad dielectric layer to expose top surface of the contact pad and causes the top surface of pad dielectric layer to be slightly below the top surface of the pad interconnect.

### Claim 12 (depends on 11)

The method of claim 11 wherein the flowable dielectric material comprises PETEOS/BPSG, polyimide or a combination thereof.

### Claim 13 (depends on 9)

The method of claim 9 wherein:
forming the passivation layer is performed after forming the upper pad dielectric layer; and comprising
patterning the passivation layer and upper pad dielectric layer to expose a top surface of the contact pad.

### Claim 14 (depends on 9)

The method of claim 9 comprising:
performing a planarization process to reduce thickness of the upper pad dielectric layer to a desired thickness, wherein the planarization process forms a planar top surface, leaving a thin upper dielectric layer over the contact pad; and wherein
forming the passivation layer is performed after performing the planarization process.

### Claim 15 (depends on 14)

The method of claim 14 comprising patterning the passivation and upper pad dielectric layers to expose a top surface of the contact pad, wherein the top surfaces of the pad dielectric layer and the passivation layer are planar.

### Claim 16 (depends on 9)

The method of claim 9 wherein:
forming the upper pad dielectric layer comprises forming the SOG layer covering the lower pad dielectric layer and the contact pad, creating a step surface profile; and comprising
performing a planarization process to reduce thickness of the SOG layer such that a thickness of the planarized SOG layer is substantially the same as a thickness of the contact pad; and
patterning the passivation layer and upper pad dielectric layer to expose a top surface of the contact pad after performing the planarization process.

### Claim 17

A method for forming a device comprising:
providing a substrate having circuit component and a dielectric layer over the substrate, wherein the dielectric layer comprises a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer comprises at least one interconnect;
providing a pad dielectric layer which comprises a flowable dielectric material over the uppermost ILD layer;
forming a pad interconnect which is a wire bond pad configured for receiving a wire bond in the pad dielectric layer and a top surface of the pad interconnect is exposed such that the wire bond is to be attached and in direct contact thereto, wherein the pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer, wherein a top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect; and
forming a passivation layer over and in direct contact with the pad dielectric layer, wherein the passivation layer comprises a non-planar top surface having a first height closer to the pad interconnect and a second height away from the pad interconnect, wherein the first height is slightly higher than the second height, and the passivation layer is used for preventing a top surface of the pad interconnect from oxidation/corrosion and contamination during wire bonding and packaging process.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
providing the pad dielectric layer comprises forming a lower pad dielectric layer over the uppermost dielectric layer; and wherein
forming the pad interconnect comprises
forming a pad via contact opening in the lower pad dielectric layer,
forming a conductive layer on the substrate, wherein the conductive layer fills the pad via opening and covering the lower pad dielectric layer, and
patterning the conductive layer to form the pad interconnect having a contact pad over the lower pad dielectric layer and a pad via contact in the pad via opening.

### Claim 19 (depends on 18)

The method of claim 18 wherein providing the pad dielectric layer further comprises forming an upper pad dielectric layer which comprises a spin on glass (SOG) layer over the lower pad dielectric layer and covers the contact pad, creating a step surface profile.

### Claim 20 (depends on 19)

The method of claim 19 comprising performing a planarization process to remove a portion of the SOG layer over the contact pad to cause a top surface of the upper dielectric layer to be slightly below a top surface of the contact pad, thereby creating a small step profile between the upper pad dielectric layer and the contact pad.