# US 9,520,369 B2 · Power module and method of packaging the same

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- Number: US 9,520,369 B2
- Document ID: US9520369B2
- Status: Granted
- Kind: B2
- Application number: 14/925,266
- Filed: 2015-10-28
- Published: 2016-04-28
- Granted: 2016-12-13
- Earliest claimed: 2014-10-28
- Assignees: Hyundai Mobis Co., Ltd.
- Applicants: HYUNDAI MOBIS Co., Ltd.
- Inventors: Jae Hyun Ko
- Web page: https://patentgrep.com/patent/US9520369B2

## CPC

- H10W 72/00: Interconnections or connectors in packages
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/468: {Circuit boards}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07351: {characterised by changes in properties of the die-attach connectors during connecting}
- H10W 72/07354: {changes in dispositions}
- H10W 72/30: Die-attach connectors
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/381: {Auxiliary members}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a power module having an integrated power semiconductor and a method of packaging the same. The power module according to an aspect of the present invention includes a power semiconductor chip based on silicon and insulating substrates respectively disposed at both surfaces of the power semiconductor chip and including a metal pattern electrically and directly connected to the power semiconductor chip.

## Claims

### Claim 1

A power module comprising:
a power semiconductor chip based on silicon;
an upper insulating substrate disposed on an upper surface of the power semiconductor chip;
a pattern formed on a first surface of the upper insulating substrate, the pattern being electrically and directly connected to the power semiconductor chip; and
a dielectric layer formed on a second surface of the upper insulating substrate, the second surface being opposite of the first surface.

### Claim 2 (depends on 1)

The power module of claim 1, further comprising a lower insulating substrate disposed on a lower surface of the power semiconductor chip.

### Claim 3 (depends on 1)

The power module of claim 1, wherein the insulating substrates are directly connected to the power semiconductor chip via solder.

### Claim 4 (depends on 2)

The power module of claim 2, wherein the pattern is a metal wiring pattern.

### Claim 5 (depends on 4)

The power module of claim 4, wherein the upper insulating substrate further comprises:
an inner portion, wherein the pattern is disposed on a surface of the inner portion; and
an outer portion electrically connected to a power device outside of a package.

### Claim 6 (depends on 4)

The power module of claim 4, wherein the pattern is made of any one of copper, copper alloy, nickel plated copper, aluminum, or aluminum alloy.

### Claim 7 (depends on 1)

The power module of claim 1, further comprising:
a heat sink layer configured to cover the second surface; and
a heat sink attached to the heat sink layer via solder.

### Claim 8

A method of packaging a power module, comprising:
forming a pattern on a first surface of an upper insulating substrate;
disposing a power semiconductor chip based on silicon under the upper insulating substrate;
disposing and bonding a lower insulating substrate under the power semiconductor chip; and
forming a dielectric layer on a second surface of the upper insulating substrate opposite the first surface.

### Claim 9 (depends on 8)

The method of claim 8, wherein the pattern is a metal pattern electrically and directly connected to the power semiconductor chip.

### Claim 10 (depends on 9)

The method of claim 9, wherein the pattern is made of any one of copper, copper alloy, nickel plated copper, aluminum, or aluminum alloy.

### Claim 11 (depends on 8)

The method of claim 8, wherein an outer portion of the upper insulating substrate is electrically connected to a power device outside a package.

### Claim 12 (depends on 8)

The method of claim 8, wherein the insulating substrates and the power semiconductor chip are directly attached via solder.

### Claim 13 (depends on 8)

The method of claim 8, wherein the disposing and bonding the lower insulating substrate further comprises forming a heat sink layer configured to cover the second surface, and attaching a heat sink.

### Claim 14

A power module comprising:
a power semiconductor chip based on silicon;
an upper insulating substrate disposed on an upper surface of the power semiconductor chip;
a pattern formed on a first surface of the upper insulating substrate, the pattern being electrically and directly connected to the power semiconductor chip;
a dielectric layer formed on a second surface of the upper insulating substrate, the second surface being opposite of the first surface;
a heat sink layer configured to cover the second surface; and
a heat sink attached to the heat sink layer using solder.