# US 9,520,367 B2 · Trenched Faraday shielding

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- Number: US 9,520,367 B2
- Document ID: US9520367B2
- Status: Granted
- Kind: B2
- Application number: 14/463,982
- Filed: 2014-08-20
- Published: 2016-02-25
- Granted: 2016-12-13
- Earliest claimed: 2014-08-20
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Zihao M. Gao; David C. Burdeaux; Wayne R. Burger; Robert A. Pryor; Philippe Renaud
- Inventors: Zihao M. Gao; David C. Burdeaux; Wayne R. Burger; Robert A. Pryor; Philippe Renaud
- Web page: https://patentgrep.com/patent/US9520367B2

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/655: {having edge termination structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/111: {Field plates}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 84/151: {LDMOS having built-in components}
- H10P 14/40: of conductive or resistive materials
- H10P 50/642: {Chemical etching}
- H10W 20/423: {Shielding layers}
- H10W 29/00: Generic parts of integrated devices, not otherwise provided for
- H10W 29/01: {Manufacture or treatment}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.

## Claims

### Claim 1

A device comprising:
a semiconductor substrate having a surface with a trench;
first and second conduction terminals supported by the semiconductor substrate;
a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals; and
a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal;
wherein the trench is laterally spaced from the control electrode by a lateral spacing,
wherein the Faraday shield comprises a first portion that extends laterally above the surface of the semiconductor substrate across the lateral spacing and a second portion that extends laterally in the trench,
wherein the Faraday shield is plate-shaped such that the second portion has upper and lower surfaces that conform to a topography of the trench, and
wherein the Faraday shield is not electrically connected to the control electrode.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a doped region in the semiconductor substrate having a conductivity type to allow the charge carriers to drift through the doped region under an electric field arising from a bias voltage applied between the first and second conduction terminals during operation, wherein the trench is disposed in the doped region.

### Claim 3 (depends on 2)

The device of claim 2, wherein:
the doped region comprises a first section in which the trench is disposed and a second section disposed between the first section and the second conduction terminal;
a lower boundary of the first section is deeper than a lower boundary of the second section; and
the first section has a higher dopant concentration level than the second section at a given depth.

### Claim 4 (depends on 1)

The device of claim 1, wherein the trench has a cross-sectional shape selected from a V-shaped cross-section and a U-shaped cross-section.

### Claim 5

A device comprising:
a semiconductor substrate having a surface with a trench;
first and second conduction terminals supported by the semiconductor substrate;
a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals; and
a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal;
wherein the trench is laterally spaced from the control electrode by a lateral spacing,
wherein the Faraday shield comprises a first portion that extends laterally above the surface of the semiconductor substrate across the lateral spacing and a second portion that extends laterally in the trench,
wherein the Faraday shield is not electrically connected to the control electrode, and
wherein the second portion of the Faraday shield extends laterally in parallel with a bottom of the trench, and wherein the second portion of the Faraday shield extends less than an entire lateral extent of the trench.

### Claim 6 (depends on 1)

The device of claim 1, wherein the portion of the Faraday shield extends an entire lateral extent of the trench.

### Claim 7 (depends on 1)

The device of claim 1, further comprising a further Faraday shield extending over the trench above the first-named Faraday shield.

### Claim 8 (depends on 1)

The device of claim 1, wherein the Faraday shield extends laterally over the control electrode.

### Claim 9

A device comprising:
a semiconductor substrate having a surface with a trench;
first and second conduction terminals supported by the semiconductor substrate;
a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals; and
a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal;
wherein the trench is laterally spaced from the control electrode by a lateral spacing,
wherein the Faraday shield comprises a first portion that extends laterally above the surface of the semiconductor substrate across the lateral spacing and a second portion that extends laterally in the trench,
wherein the Faraday shield is not electrically connected to the control electrode, and
wherein the trench is spaced from the second conduction terminal such that the trench is closer to the control electrode than to the second conduction terminal.

### Claim 10 (depends on 1)

The device of claim 1, wherein the first and second conduction terminals are asymmetrically arranged about the control electrode.

### Claim 11 (depends on 1)

The device of claim 1, wherein the semiconductor substrate comprises an epitaxial layer that establishes the surface with the trench.

### Claim 12

An electronic apparatus comprising:
a semiconductor substrate having a surface with a trench; and
a transistor structure comprising a transistor body region disposed in the semiconductor substrate, the transistor structure further comprising:
source and drain terminals supported by the semiconductor substrate;
a gate structure supported by the semiconductor substrate between the source and drain terminals and configured to control current flow during operation between the source and drain terminals through the transistor body region; and
a shield plate disposed between the gate structure and the drain terminal;
wherein the trench is laterally spaced from the gate structure by a lateral spacing,
wherein the shield plate comprises a first portion that extends laterally above the surface of the semiconductor substrate across the lateral spacing and a second portion that extends laterally in the trench at a height lower than the gate structure,
wherein the shield plate is plate-shaped such that the second portion has upper and lower surfaces that conform to a topography of the trench, and
wherein the shield plate is not electrically connected to the gate structure.

### Claim 13 (depends on 12)

The electronic apparatus of claim 12, further comprising a composite drift region disposed in the semiconductor substrate and having a conductivity type to allow charge carriers to drift through the drift region under an electric field arising from a bias voltage applied between the source and drain terminals during operation, wherein:
the composite drift region comprises a first section in which the trench is disposed and a second section disposed between the first section and the drain terminal; and
a lower boundary of the first section is deeper than a lower boundary of the second section.

### Claim 14 (depends on 12)

The electronic apparatus of claim 12, further comprising a composite drift region disposed in the semiconductor substrate and having a conductivity type to allow charge carriers to drift through the drift region under an electric field arising from a bias voltage applied between the source and drain terminals during operation, wherein:
the composite drift region comprises a first section in which the trench is disposed and a second section disposed between the first section and the drain terminal; and
the first section has a higher dopant concentration level than the second section at a given depth.

### Claim 15 (depends on 12)

The electronic apparatus of claim 12, wherein the trench is spaced from the drain terminal such that the trench is closer to the gate structure than to the drain terminal.

### Claim 16

A method of fabricating a transistor, the method comprising:
forming a control electrode of the transistor on a surface of a semiconductor substrate;
implanting dopant in the semiconductor substrate to form first and second conduction terminal regions at the surface of the semiconductor substrate, the first conduction terminal region being adjacent to the control electrode, and the second conduction terminal region being spaced from the control electrode;
etching a trench in the surface of the semiconductor substrate, wherein the trench is laterally spaced from the control electrode by a lateral spacing;
forming a Faraday shield on the surface of the semiconductor substrate, wherein the Faraday shield comprises a first portion that extends laterally above the surface of the semiconductor substrate across the lateral spacing and a second portion that extends laterally in the trench at a height lower than the control electrode, and wherein the Faraday shield is plate-shaped such that the second portion has upper and lower surfaces that conform to a topography of the trench; and
depositing a dielectric layer between the Faraday shield and the control electrode such that the Faraday shield is not electrically connected to the control electrode.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
performing a first dopant implantation to form a drift region in the semiconductor substrate that extends from the control electrode to the second conduction terminal region to allow charge carriers to drift through the drift region under an electric field arising from a bias voltage applied between the first and second conduction terminal regions during operation; and
performing a second dopant implantation to increase a dopant concentration level of the drift region along sidewalls of the trench and under the trench.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second dopant implantation is configured as an angled implantation.

### Claim 19 (depends on 17)

The method of claim 17, wherein the second dopant implantation has an ion energy sufficient to deepen a lower boundary of the drift region under the trench.

### Claim 20

A method of fabricating a transistor, the method comprising:
forming a control electrode of the transistor on a surface of a semiconductor substrate;
implanting dopant in the semiconductor substrate to form first and second conduction terminal regions at the surface of the semiconductor substrate, the first conduction terminal region being adjacent to the control electrode, and the second conduction terminal region being spaced from the control electrode;
etching a trench in the surface of the semiconductor substrate, wherein the trench is laterally spaced from the control electrode by a lateral spacing;
forming a Faraday shield on the surface of the semiconductor substrate, wherein the Faraday shield comprises a first portion that extends laterally above the surface of the semiconductor substrate across the lateral spacing and a second portion that extends laterally in the trench at a height lower than the control electrode; and
depositing a dielectric layer between the Faraday shield and the control electrode such that the Faraday shield is not electrically connected to the control electrode;
wherein the trench is spaced from the second conduction terminal region such that the trench is closer to the control electrode than to the second conduction terminal region.