# US 9,520,365 B2 · Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers

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- Number: US 9,520,365 B2
- Document ID: US9520365B2
- Status: Granted
- Kind: B2
- Application number: 13/728,012
- Filed: 2012-12-27
- Published: 2013-06-06
- Granted: 2016-12-13
- Earliest claimed: 2011-01-21
- Assignees: STATS ChipPAC Pte. Ltd.
- Applicants: STATS ChipPAC, Ltd.
- Inventors: Yaojian Lin; Kang Chen; Yu Gu; Wei Meng; Chee Siang Ong
- Web page: https://patentgrep.com/patent/US9520365B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/40: characterised by their materials
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die including a plurality of contact pads;
a first insulating layer formed in contact with an active surface of the semiconductor die;
an encapsulant deposited over a second surface of the semiconductor die opposite the active surface and in a peripheral region around the semiconductor die; and
an interconnect structure formed over the encapsulant and first insulating layer, wherein the interconnect structure includes,
(a) a second insulating layer formed in direct contact with the encapsulant and first insulating layer, wherein a coefficient of thermal expansion (CTE) of the second insulating layer is within a first range of 30-90 parts per million (ppm),
(b) a first conductive layer formed over the second insulating layer and the plurality of contact pads,
(c) a third insulating layer formed in direct contact with the second insulating layer and first conductive layer, wherein a CTE of the third insulating layer is within a second range of 90-110 ppm,
(d) a second conductive layer formed over the second insulating layer and first conductive layer, and
(e) a fourth insulating layer formed in direct contact with the third insulating layer and second conductive layer, wherein a CTE of the fourth insulating layer is within a third range of 110-150 ppm.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second insulating layer, third insulating layer, and fourth insulating layer each have a tensile strength>100 MPa, elongation>20%, and modulus<3.0 Gpa under 25° C.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further including a bump formed over the second conductive layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second insulating layer, third insulating layer, and fourth insulating layer each include a polymer dielectric material having a less than 250° C. cure temperature.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the CTE of the second insulating layer is 73 ppm, the CTE of the third insulating layer is 106 ppm, and the CTE of the fourth insulating layer is 126 ppm.

### Claim 6

A semiconductor device, comprising:
a semiconductor die including a plurality of contact pads;
a first insulating layer formed in contact with an active surface of the semiconductor die;
an encapsulant deposited over a second surface of the semiconductor die opposite the active surface and in a peripheral region around the semiconductor die; and
an interconnect structure formed over the encapsulant and first insulating layer, wherein the interconnect structure includes,
(a) a second insulating layer formed in direct contact with the encapsulant and first insulating layer, wherein a coefficient of thermal expansion (CTE) of the second insulating layer is within a first range of 110-150 parts per million (ppm),
(b) a first conductive layer formed over the second insulating layer and the plurality of contact pads,
(c) a third insulating layer formed in direct contact with the second insulating layer and first conductive layer, wherein a CTE of the third insulating layer is within a second range of 90-110 ppm,
(d) a second conductive layer formed over the second insulating layer and first conductive layer, and
(e) a fourth insulating layer formed in direct contact with the third insulating layer and second conductive layer, wherein a CTE of the fourth insulating layer is within a third range of 30-90 ppm.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the second insulating layer, third insulating layer, and fourth insulating layer each have a tensile strength>100 MPa, elongation>20%, and modulus<3.0 Gpa under 25° C.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, further including a bump formed over the second conductive layer.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the second insulating layer, third insulating layer, and fourth insulating layer each include a polymer dielectric material having a less than 250° C. cure temperature.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the CTE of the second insulating layer is 73 ppm, the CTE of the third insulating layer is 106 ppm, and the CTE of the fourth insulating layer is 126 ppm.

### Claim 11

A semiconductor device, comprising:
a semiconductor die including a plurality of contact pads;
a first insulating layer formed in contact with a first surface of the semiconductor die;
an encapsulant deposited over a second surface of the semiconductor die opposite the first surface and in a peripheral region around the semiconductor die; and
an interconnect structure formed over the encapsulant and first insulating layer, wherein the interconnect structure includes,
(a) a second insulating layer formed in direct contact with the encapsulant and the first insulating layer, wherein a coefficient of thermal expansion (CTE) of the second insulating layer is within a first range,
(b) a first conductive layer formed over the second insulating layer and the plurality of contact pads,
(c) a third insulating layer formed in direct contact with the second insulating layer and first conductive layer, wherein a CTE of the third insulating layer is within a second range overlapping in part and different in part with respect to the first range,
(d) a second conductive layer formed over the second insulating layer and first conductive layer, and
(e) a fourth insulating layer formed in direct contact with the third insulating layer and second conductive layer, wherein a CTE of the fourth insulating layer is within a third range overlapping in part and different in part with respect to the second range.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first range is selected from the group consisting of 30-90 parts per million (ppm), 90-110 ppm, and 110-150 ppm.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the second range is selected from the group consisting of 30-90 parts per million (ppm) and 90-110 ppm.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the third range is selected from the group consisting of 30-90 parts per million (ppm), 90-110 ppm, and 110-150 ppm.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, further including a bump formed over the second conductive layer.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the second insulating layer and third insulating layer each have a tensile strength>100 MPa, elongation>20%, and modulus<3.0 Gpa under 25° C.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, wherein the second insulating layer and third insulating layer each include a polymer dielectric material having a less than 250° C. cure temperature.

### Claim 18

A semiconductor device, comprising:
a semiconductor die including a plurality of contact pads;
an encapsulant deposited over the semiconductor die opposite the first surface and in a peripheral region around the semiconductor die; and
an interconnect structure formed over the encapsulant and the semiconductor die, wherein the interconnect structure includes,
(a) a first insulating layer formed over the encapsulant and semiconductor die, wherein a coefficient of thermal expansion (CTE) of the first insulating layer is within a first range,
(b) a first conductive layer formed over the first insulating layer and the plurality of contact pads,
(c) a second insulating layer formed in direct contact with the first insulating layer and first conductive layer, wherein a CTE of the second insulating layer is within a second range overlapping in part and different in part with respect to the first range,
(d) a second conductive layer formed over the second insulating layer and first conductive layer, and
(e) a third insulating layer formed in direct contact with the second insulating layer and second conductive layer, wherein a CTE of the third insulating layer is within a third range overlapping in part and different in part with respect to the second range.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the first range is selected from the group consisting of 30-90 parts per million (ppm), 90-110 ppm, and 110-150 ppm.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the second range is selected from the group consisting of 30-90 parts per million (ppm) and 90-110 ppm.

### Claim 21 (depends on 18)

The semiconductor device of claim 18, wherein the third range is selected from the group consisting of 30-90 parts per million (ppm), 90-110 ppm, and 110-150 ppm.

### Claim 22 (depends on 18)

The semiconductor device of claim 18, further including a bump formed over the second conductive layer.

### Claim 23 (depends on 18)

The semiconductor device of claim 18, wherein the first insulating layer and second insulating layer each have a tensile strength>100 MPa, elongation>20%, and modulus<3.0 Gpa under 25° C.

### Claim 24 (depends on 18)

The semiconductor device of claim 18, wherein the first insulating layer and second insulating layer each include a polymer dielectric material having a less than 250° C. cure temperature.