# US 9,520,364 B2 · Front side package-level serialization for packages comprising unique identifiers

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- Number: US 9,520,364 B2
- Document ID: US9520364B2
- Status: Granted
- Kind: B2
- Application number: 14/836,525
- Filed: 2015-08-26
- Published: 2016-03-03
- Granted: 2016-12-13
- Earliest claimed: 2014-08-26
- Assignees: DECA Technologies Inc.
- Applicants: DECA Technologies Inc.
- Inventors: Craig Bishop; Sabbas A. Daniel; Christopher M. Scanlan
- Web page: https://patentgrep.com/patent/US9520364B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10W 20/01: {Manufacture or treatment}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/0198: {batch processes}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 46/103: {alphanumeric information, e.g. words, letters or serial numbers}
- H10W 46/106: {digital information, e.g. bar codes}
- H10W 46/401: {for identification or tracking}
- H10W 46/603: {Formed on wafers or substrates before dicing and remaining on chips after dicing}
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01257: {by reflowing}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making a semiconductor device can include providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. The method can include forming a build-up interconnect structure that extends over the active surface of each of the plurality of semiconductor die within the wafer, and forming a unique identifying mark for each of the plurality of semiconductor die as part of a layer within the build-up interconnect structure while simultaneously forming the layer of the build-up interconnect structure. The layer of the build-up interconnect structure can comprise both the unique identifying marks for each of the plurality of semiconductor die and functionality for the semiconductor device. Each unique identifying mark can convey a unique identity of its respective semiconductor die. The method can further include singulating the plurality of semiconductor die into a plurality of semiconductor devices.

## Claims

### Claim 1

A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die within a wafer, wherein each semiconductor die comprises an active surface and a backside opposite the active surface;
forming a build-up interconnect structure that extends over the active surface of each of the plurality of semiconductor die within the wafer;
forming a unique identifying mark for each of the plurality of semiconductor die as part of a layer within the build-up interconnect structure while simultaneously forming the layer of the build-up interconnect structure, wherein the layer of the build-up interconnect structure comprises both the unique identifying marks for each of the plurality of semiconductor die and functionality for the semiconductor device, wherein each unique identifying mark conveys a unique identity of its respective semiconductor die; and
singulating the plurality of semiconductor die into a plurality of semiconductor devices.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming the layer of the build-up interconnect structure as a conductive layer;
forming the unique identifying mark for each of the plurality of semiconductor die as a first portion of the conductive layer; and
forming a second portion of the conductive layer as a redistribution layer (RDL).

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming the unique identifying mark for each of the plurality of semiconductor die within the build-up interconnect structure and away from an exterior surface of the semiconductor package such that the unique identifying mark for each of the plurality of semiconductor die are not subject to damage at an exterior surface of the semiconductor package.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming the unique identifying mark for each of the plurality of semiconductor die within the build-up interconnect structure in a position that is optically detectable from an exterior of the semiconductor device.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming the unique identifying mark as a machine-readable 2-dimensional code or an alpha-numeric mark.

### Claim 6 (depends on 1)

The method of claim 1, wherein the unique identity of the semiconductor die conveyed by each of the respective unique identifying marks comprises source wafer identification, and the x, y location of the semiconductor die within the wafer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the information conveyed by each of the respective unique identifying marks further comprises a reconstituted wafer or panel identification and an x, y location of the semiconductor device within the reconstituted wafer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming the reconstituted wafer by disposing an encapsulant around the plurality of semiconductor die before forming the build-up interconnect structure.

### Claim 9

A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface;
forming a functional layer as part of a build-up interconnect structure that extends over the active surface of each of the plurality of semiconductor die, the functional layer further comprising a unique identifying mark for each of the plurality of semiconductor die simultaneously with forming the build-up interconnect structure, wherein each unique identifying mark conveys a unique identity of its respective semiconductor die; and
singulating the plurality of semiconductor die.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming the unique identifying mark for each of the plurality of semiconductor die as a first portion of the build-up interconnect structure; and
forming a second portion of the build-up interconnect structure as a redistribution layer (RDL).

### Claim 11 (depends on 9)

The method of claim 9, further comprising forming the unique identifying mark and the functional layer in the build-up structure with a maskless patterning system.

### Claim 12

A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface;
forming a functional layer that extends over the active surface of each of the plurality of semiconductor die, the functional layer further comprising a unique identifying mark for each of the plurality of semiconductor die, wherein each unique identifying mark conveys a unique identity of its respective semiconductor die, wherein forming the unique identifying marks further comprises forming the unique identifying mark for each of the plurality of semiconductor die away from an exterior surface of a semiconductor package such that the unique identifying mark for each of the plurality of semiconductor die are not subject to damage at an exterior surface of the semiconductor package; and
singulating the plurality of semiconductor die.

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming the unique identifying mark for each of the plurality of semiconductor die in a position that is optically detectable from an exterior of the semiconductor device.

### Claim 14 (depends on 9)

The method of claim 9, further comprising forming the unique identifying mark as a machine-readable barcode or 2-dimensional matrix.

### Claim 15 (depends on 9)

The method of claim 9, wherein the unique identity of the semiconductor die conveyed by each of the respective unique identifying marks comprises source wafer identification, an x, y location of the semiconductor die within a source wafer, a reconstituted wafer or panel identification, and an x, y location of the semiconductor device within the reconstituted wafer.

### Claim 16 (depends on 14)

The method of claim 14, further comprising forming a reconstituted wafer by disposing an encapsulant around the plurality of semiconductor die before forming the functional layer.

### Claim 17 (depends on 9)

The method of claim 9, further comprising interpreting the unique identifying mark of the semiconductor package to derive the unique identity of the semiconductor device.

### Claim 18

A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface;
forming a build-up interconnect structure or functional layer that extends over each of the plurality of semiconductor die, the build-up interconnect structure further comprising:
a first portion comprising a unique identifying mark for each of the plurality of semiconductor die, wherein each unique identifying mark conveys information about its respective semiconductor die, and
a second portion formed as a redistribution layer (RDL); and
singulating the plurality of semiconductor die.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming the unique identifying mark for each of the plurality of semiconductor die when forming the build-up interconnect structure.

### Claim 20 (depends on 18)

The method of claim 18, wherein each unique identifying mark conveys a unique identity of its respective semiconductor die.

### Claim 21 (depends on 18)

The method of claim 18, further comprising forming the unique identifying mark and the RDL in the build-up structure with a maskless patterning system.

### Claim 22 (depends on 18)

The method of claim 18, further comprising forming the unique identifying mark for each of the plurality of semiconductor die away from an exterior surface of a semiconductor package such that the unique identifying mark for each of the plurality of semiconductor die are not subject to damage at an exterior surface of the semiconductor package.

### Claim 23 (depends on 18)

The method of claim 18, further comprising forming the unique identifying mark for each of the plurality of semiconductor die in a position that is optically detectable from an exterior of the semiconductor device.

### Claim 24 (depends on 18)

The method of claim 18, wherein the unique identity of the semiconductor die conveyed by each of the respective unique identifying marks comprises one or more of a source wafer identification, an x, y location of the semiconductor die within a source wafer, a reconstituted wafer or panel identification, and an x, y location of the semiconductor device within the reconstituted wafer.