# US 9,520,362 B2 · Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components

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- Number: US 9,520,362 B2
- Document ID: US9520362B2
- Status: Granted
- Kind: B2
- Application number: 14/706,311
- Filed: 2015-05-07
- Published: 2015-08-20
- Granted: 2016-12-13
- Earliest claimed: 2011-06-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Chieh Lin; Hung-Wen Su; Ming-Hsing Tsai; Syun-Ming Jang
- Web page: https://patentgrep.com/patent/US9520362B2

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/086: {involving buried masks}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/48: Insulating materials thereof
- H10P 14/46: using a liquid
- H10W 20/0886: {involving forming a via in a via-level dielectric prior to deposition of a trench-level dielectric}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first interconnect layer disposed over the substrate;
a second interconnect layer disposed over the first interconnect layer, wherein: the second interconnect layer includes a plurality of dielectric segments, a plurality of metal line components interleaving with the dielectric segments, and a plurality of dielectric barrier elements disposed between the dielectric segments and the metal line components;
a plurality of vias disposed underneath a first subset of the metal line components;
a plurality of dielectric components interleaving with the plurality of vias, wherein the dielectric components are disposed underneath a second subset of the metal line components different from the first subset, and wherein the plurality of vias and the plurality of dielectric components are disposed over the first interconnect layer; and
an etch-stop layer disposed above the first interconnect layer but below the plurality of vias and the plurality of dielectric components.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric barrier elements contain a compound that is made of a plurality of elements selected from the group consisting of: Si, O, C, N, and B.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric barrier elements are each shaped as a recess, and wherein each of the dielectric segments is disposed in a respective one of recesses.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising an interlayer dielectric (ILD) layer disposed between the substrate and the first interconnect layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first interconnect layer contains a plurality of further dielectric segments, a plurality of further metal line components interleaving with the further dielectric segments, and a plurality of further dielectric barrier elements disposed between the further dielectric segments and the further metal line components.

### Claim 6

A semiconductor device, comprising:
a substrate;
an interlayer dielectric (ILD) layer disposed over the substrate;
a first interconnect layer disposed over the ILD layer, wherein the first interconnect layer contains a plurality of first dielectric segments, a plurality of first metal line components interleaving with the first dielectric segments, and a plurality of first dielectric barrier elements disposed between the first dielectric segments and the first metal line components; and
a second interconnect layer disposed over the first interconnect layer, wherein the second interconnect layer contains a plurality of second dielectric segments, a plurality of second metal line components interleaving with the second dielectric segments, and a plurality of second dielectric barrier elements disposed between the second dielectric segments and the second metal line components;
a plurality of vias disposed between a subset of the first metal line components and a subset of the second metal line components; and
a plurality of third dielectric segments disposed between the first dielectric segments and the second dielectric segments, wherein the third dielectric segments and the second dielectric segments are separated by portions of the second dielectric barrier elements, wherein a first portion of each of the vias is surrounded by the second dielectric segments adjacent to the via, and a second portion of each of the vias is surrounded by the third dielectric segments adjacent to the via.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein:
the first dielectric barrier elements and the second dielectric barrier elements each contain a compound that is made of a plurality of elements selected from the group consisting of: Si, O, C, N, and B; and
the first dielectric barrier elements and the second dielectric barrier elements form recesses in which the first dielectric segments and the second dielectric segments are disposed, respectively.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein each of the vias is disposed between a respective one of the first metal line components and a respective one of the second metal line components.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, further comprising an etch-stop layer disposed between the first interconnect layer and the second interconnect layer.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein each of the vias has a conductive liner disposed on its sidewalls, wherein conductive liners are not disposed on sidewalls of the plurality of the second metal line components.

### Claim 11 (depends on 6)

The semiconductor device of claim 6, wherein a bottom surface of each of the second dielectric segments is located lower than a bottom surface of each of the second metal line components.

### Claim 12 (depends on 6)

The semiconductor device of claim 6, wherein the second dielectric segments and the second metal line components have co-planar upper surfaces.

### Claim 13

A semiconductor device, comprising:
a layer containing a plurality of conductive barrier segments interdigitated with a plurality of etching-stop segments;
a plurality of first dielectric segments disposed over the etching-stop segments, respectively;
a plurality of conductive liner segments disposed over the conductive barrier segments, respectively, wherein portions of the conductive liner segments are disposed along sidewalls of adjacent first dielectric segments;
a plurality of dielectric barrier segments disposed over the first dielectric segments, respectively, wherein the dielectric barrier segments contain a plurality of openings, and wherein each dielectric barrier segment of at least a subset of the plurality of the dielectric barrier segments has a sidewall that is partially contiguous with a sidewall of an adjacent conductive liner segment;
a plurality of second dielectric segments filling the openings, respectively;
a plurality of vias disposed over bottom portions of the conductive liner segments, respectively; and
a plurality of metal line components, wherein each metal line component of a first subset of the metal line components is disposed over a respective one of the vias, and each metal line component of a second subset of the metal line components is disposed over a respective one of the first dielectric segments.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the plurality of metal line components are interdigitated with the second dielectric segments.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein:
the conductive liner segments each include a metal material that is free of copper; and
the conductive barrier segments each include a material selected from the group consisting of: tantalum, tantalum nitride, titanium, titanium nitride, and manganese oxide.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein each conductive barrier segment and each conductive liner segment are no thicker than about 50 Angstroms.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, further including:
a substrate;
an interlayer dielectric (ILD) layer disposed over the substrate; and
an interconnect layer disposed over the ILD layer, the interconnect layer containing a plurality of further metal line components;
wherein the layer containing the conductive barrier segments is disposed over the interconnect layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the interconnect layer further includes:
a plurality of further conductive barrier segments disposed over the ILD layer;
a plurality of further conductive liner segments disposed over the further conductive barrier segments, respectively;
a plurality of further dielectric barrier segments disposed over the ILD layer, the further dielectric barrier segments containing a plurality of further openings; and
a plurality of third dielectric segments filling the further openings, respectively;
wherein:
the further metal line components are disposed over the further conductive liner segments, respectively; and
the further metal line components are interdigitated with the third dielectric segments.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein:
the first, second, and third dielectric segments all contain a low-k dielectric material; and
the dielectric barrier segments all contain a material that is a compound, the compound being made of a plurality of elements selected from the group consisting of: silicon, oxygen, carbon, nitride, and boron.

### Claim 20 (depends on 13)

The semiconductor device of claim 13, wherein a portion of each of the second dielectric barrier elements is in physical contact with the conductive liner.