# US 9,520,361 B2 · Semiconductor devices

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- Number: US 9,520,361 B2
- Document ID: US9520361B2
- Status: Granted
- Kind: B2
- Application number: 14/937,406
- Filed: 2015-11-10
- Published: 2016-05-19
- Granted: 2016-12-13
- Earliest claimed: 2014-11-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Pil-Kyu Kang; Seok-Ho Kim; Tae-Yeong Kim; Hyo-Ju Kim; Byung-Lyul Park; Joo-Hee Jang; Jin-Ho Chun
- Web page: https://patentgrep.com/patent/US9520361B2

## CPC

- H10W 20/4421: {the principal metal being copper}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/026: {Wafer-level processing}
- H10F 39/8053: {Colour filters}
- H10F 39/8057: {Optical shielding}
- H10F 39/8063: {Microlenses}
- H10F 39/8067: {Reflectors}
- H10F 39/809: {of hybrid image sensors}
- H10F 39/811: {Interconnections}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 72/00: Interconnections or connectors in packages
- H10W 90/00: Package configurations
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 80/016: {Cleaning}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first insulating interlayer on the substrate;
a first conductive pattern structure in the first insulating interlayer, the first conductive pattern structure protruding upwardly beyond a top surface of the first insulating interlayer;
a first diffusion blocking insulation layer on the first insulating interlayer, the first diffusion blocking insulation layer on an upper portion of a sidewall of the first conductive pattern structure that protrudes beyond the first insulating interlayer;
a first bonding layer on the first diffusion blocking insulation layer, the first bonding layer on the upper portion of the sidewall of the first conductive pattern structure that protrudes beyond the first insulating interlayer;
a first shield pattern in the first bonding layer, the first shield pattern being spaced apart from the first conductive pattern structure and surrounding the first conductive pattern structure;
a second bonding layer on the first bonding layer and the first shield pattern;
a second diffusion blocking insulation layer on the second bonding layer;
a second insulating interlayer on the second diffusion blocking insulation layer;
a second conductive pattern structure in the second insulating interlayer, the second diffusion blocking insulation layer, and the second bonding layer, the second conductive pattern structure contacting a top surface of the first conductive pattern structure; and
a second shield pattern in the second bonding layer, the second shield pattern being spaced apart from the second conductive pattern structure and surrounding the second conductive pattern structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first and second shield patterns contact each other.

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein the first conductive pattern structure comprises:
a first barrier layer pattern on sidewalls of the first insulating interlayer, the first diffusion blocking insulation layer, and the first bonding layer, respectively; and
a first conductive pattern,
wherein the first barrier layer pattern is on a sidewall and a bottom surface of the first conductive pattern,
wherein the second conductive pattern structure comprises:
a second barrier layer pattern on sidewalls of the second insulating interlayer, the second diffusion blocking insulation layer, and the second bonding layer, respectively; and
a second conductive pattern, and
wherein the second barrier layer pattern is on a sidewall and a top surface of the second conductive pattern.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first and second barrier layer patterns and the first and second shield patterns each comprise a metal, a metal nitride, or a metal alloy.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein each of the first and second conductive patterns comprises copper, aluminum, tungsten, and/or nickel.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third insulating interlayer between the substrate and the first insulating interlayer, the third insulating interlayer comprising a third conductive pattern structure therein that contacts the first conductive pattern structure; and
a fourth insulating interlayer on the second insulating interlayer, the fourth insulating interlayer comprising a fourth conductive pattern structure therein that contacts the second conductive pattern structure.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising:
a first etch stop layer between the first and third insulating interlayers, the first etch stop layer on a lower portion of the sidewall of the first conductive pattern structure; and
a second etch stop layer between the second and fourth insulating interlayers, the second etch stop layer on an upper portion of a sidewall of the second conductive pattern structure.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first conductive pattern structure contacts the second bonding layer, and the second conductive pattern structure contacts the first bonding layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first shield pattern comprises a plurality of first shield patterns spaced apart from each other in the first bonding layer, and the second shield pattern comprises a plurality of second shield patterns spaced apart from each other in the second bonding layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein at least one of the plurality of first shield patterns and at least one of the plurality of second shield patterns contact each other.

### Claim 11

A semiconductor device, comprising:
a substrate;
a first insulating interlayer on the substrate;
a first conductive connector in the first insulating interlayer, the first conductive connector protruding upwardly beyond a top surface of the first insulating interlayer;
a first diffusion blocking layer on the first insulating interlayer, the first diffusion blocking layer on an upper portion of a sidewall of the first conductive connector that protrudes beyond the first insulating interlayer;
a first bonding layer on the first diffusion blocking layer, the first bonding layer on the upper portion of the sidewall of the first conductive connector that protrudes beyond the first insulating interlayer;
a first shield pattern in the first bonding layer and the first diffusion blocking layer, the first shield pattern being spaced apart from and defining a perimeter around the first conductive connector;
a second bonding layer on the first bonding layer and the first shield pattern;
a second diffusion blocking layer on the second bonding layer;
a second insulating interlayer on the second diffusion blocking layer;
a second conductive connector in the second insulating interlayer, the second diffusion blocking layer, and the second bonding layer, the second conductive connector contacting a top surface of the first conductive connector; and
a second shield pattern in the second bonding layer and the second diffusion blocking layer, the second shield pattern being spaced apart from and defining a perimeter around the second conductive connector.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first and second shield patterns contact each other.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first conductive connector contacts the second bonding layer, and the second conductive connector contacts the first bonding layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first shield pattern comprises a plurality of first shield patterns spaced apart from each other in the first bonding layer and the first diffusion blocking layer, and the second shield pattern comprises a plurality of second shield patterns spaced apart from each other in the second bonding layer and the second diffusion blocking layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein at least one of the plurality of first shield patterns and at least one of the plurality of second shield patterns contact each other.

### Claim 16

A semiconductor device comprising:
a substrate;
a first conductive structure on the substrate;
a second conductive structure on the first conductive structure;
an insulating interlayer on a sidewall of the first conductive structure, the insulating interlayer including an oxide;
first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures, the first and second metal-diffusion-blocking layers including a nitride, and the first metal-diffusion-blocking layer being on the insulating interlayer;
an insulating layer between the first and second metal-diffusion-blocking layers, the insulating layer including a nitride; and
a first metal-diffusion-shield pattern extending in both of the insulating layer and the first metal-diffusion-blocking layer, the first metal-diffusion-shield pattern being spaced apart from the first conductive structure.

### Claim 17 (depends on 16)

The semiconductor device of claim 16,
wherein a portion of the insulating layer extends under a portion of the second conductive structure.

### Claim 18 (depends on 17)

The semiconductor device of claim 17,
wherein the portion of the insulating layer is between the portion of the second conductive structure and a portion of the first metal-diffusion-blocking layer that extends under the portion of the second conductive structure, and
wherein a first width of the first conductive structure substantially equals a second width of the second conductive structure.

### Claim 19 (depends on 18)

The semiconductor device of claim 18,
further comprising a second metal-diffusion-shield pattern that contacts a portion of the first metal-diffusion-shield pattern, the second metal-diffusion-shield pattern extending in both of the insulating layer and the second metal-diffusion-blocking layer,
wherein the first metal-diffusion-shield pattern and the second metal-diffusion-shield pattern comprise a nitride.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the first and second metal-diffusion-blocking layers include silicon nitride (SiN), and the insulating layer includes silicon carbonitride (SiCN).