# US 9,520,360 B2 · Angled ion beam processing of heterogeneous structure

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- Number: US 9,520,360 B2
- Document ID: US9520360B2
- Status: Granted
- Kind: B2
- Application number: 15/131,332
- Filed: 2016-04-18
- Published: 2016-08-11
- Granted: 2016-12-13
- Earliest claimed: 2014-12-05
- Assignees: Varian Semiconductor Equipment Associates, Inc.
- Applicants: Varian Semiconductor Equipment Associates, Inc.
- Inventors: Anthony Renau; Christopher Hatem
- Web page: https://patentgrep.com/patent/US9520360B2

## CPC

- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 50/242: {of Group IV materials}
- H10P 50/263: {of silicon-containing layers}
- H10P 50/282: {of inorganic materials}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10P 50/268: {of silicon-containing layers}
- H10P 50/283: {by chemical means}
- H10P 50/667: {by liquid etching only}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a multilayer structure includes providing a mask on a device stack disposed on the substrate, the device stack comprising a first plurality of layers composed of a first layer type and a second layer type; directing first ions along a first direction forming a first non-zero angle of incidence with respect to a normal to a plane of the substrate, wherein a first sidewall is formed having a sidewall angle forming a first non-zero angle of inclination with respect to the normal, the first sidewall comprising a second plurality of layers from at least a portion of the first plurality of layers and composed of the first layer type and second layer type; and etching the second plurality of layers using a first selective etch wherein the first layer type is selectively etched with respect to the second layer type.

## Claims

### Claim 1

A semiconductor device, comprising:
a heterogeneous device stack disposed on a substrate, the heterogeneous device stack comprising a first layer type and a second layer type;
a first sidewall, the first sidewall comprising the first layer type and second layer type and defining a first average sidewall angle having a non-zero angle of inclination with respect to a normal to a plane defined by the substrate; and
a second sidewall, the second sidewall comprising the first layer type and second layer type and defining a second average sidewall angle different from the first average sidewall angle,
wherein the first sidewall comprises a stepped structure.

### Claim 2 (depends on 1)

The multilayer device of claim 1, wherein the second average sidewall angle is parallel to the normal.

### Claim 3 (depends on 1)

The multilayer device of claim 1, wherein the heterogeneous device stack comprises a vertical NAND memory device (VNAND).

### Claim 4

A multilayer semiconductor device, comprising:
a heterogeneous device stack disposed on a substrate, the heterogeneous device stack comprising a first layer of a first layer type and a second layer of a second layer type, the heterogeneous device stack comprising four sides;
wherein a first side of the four sides comprises a plurality of stepped surfaces, the plurality of stepped surfaces formed from the first layer and the second layer and defining a first average sidewall angle having a non-zero angle of inclination with respect to a normal to a plane defined by the substrate; and
wherein a second side of the four sides extends along the normal to the plane defined by the substrate.

### Claim 5 (depends on 4)

The multilayer device of claim 4, wherein the heterogeneous device stack comprises a vertical NAND memory device (VNAND) having a first plurality of layers of the first layer type and a second plurality of layers of the second layer type to serve as storage elements.

### Claim 6 (depends on 4)

The multilayer semiconductor device of claim 4, wherein:
a third side and a fourth side of the four sides extend along the normal to the plane defined by the substrate.

### Claim 7 (depends on 4)

The multilayer semiconductor device of claim 4, wherein:
a third side defines a second average sidewall angle different from the first average sidewall angle, the third side not extending along the normal.

### Claim 8 (depends on 4)

The multilayer semiconductor device of claim 4, wherein the first average sidewall angle defines a non-zero angle of inclination with respect to the normal of less than sixty degrees.

### Claim 9 (depends on 8)

The multilayer semiconductor device of claim 8, wherein the first average sidewall angle defines a non-zero angle of inclination with respect to the normal of fifteen degrees to thirty degrees.

### Claim 10 (depends on 4)

The multilayer device of claim 4, wherein the heterogeneous device stack comprises:
a third side of the four sides having a plurality of stepped surfaces and defining the first average sidewall angle; and
a fourth side of the four sides extending along the normal.

### Claim 11 (depends on 10)

The multilayer device of claim 10, further comprising a plurality of additional heterogeneous device stacks, the plurality of additional heterogeneous devices stacks comprising four side sides and further comprising:
a first layer of the first layer type and second layer of the second layer type;
first two sides side of the four sides having a plurality of stepped surfaces and defining the first average sidewall angle; and
two additional sides of the four sides extending along the normal to the substrate plane,
wherein the two additional sides of a heterogeneous device stack of the plurality of additional heterogeneous device stacks extend parallel to the second side and fourth side of the heterogeneous device stack.

### Claim 12

A multilayer semiconductor device, comprising:
a heterogeneous device stack disposed on a substrate, the heterogeneous device stack comprising a plurality of layers of a first layer type and a plurality of layers of a second layer type arranged in alternating fashion, the heterogeneous device stack comprising four sides; wherein a first side of the four sides has a plurality of stepped surfaces and defines a first average sidewall angle, the first average sidewall angle defining a non-zero angle of inclination with respect to a normal to a plane defined by the substrate, and wherein the non-zero angle of inclination is less than 60 degrees.

### Claim 13 (depends on 12)

The multilayer semiconductor device of claim 12, wherein:
the first side and a second side of the four sides have a plurality of stepped surfaces and define the first average sidewall angle having a non-zero angle of inclination with respect to the normal to a substrate plane; and wherein
a third side and a fourth side of the four sides extend along the normal.

### Claim 14 (depends on 12)

The multilayer semiconductor device of claim 12, wherein:
the four sides have a plurality of stepped surfaces and define the non-zero angle of inclination with respect to the normal.

### Claim 15 (depends on 12)

The multilayer semiconductor device of claim 12, wherein
a second side of the four sides comprises a plurality of stepped surfaces defining the first average sidewall angle; and wherein
a third side and a fourth side of the four sides define a second average sidewall angle, the second average sidewall angle differing from the first average sidewall angle, the third side and a fourth side not extending along the normal.

### Claim 16 (depends on 12)

The multilayer semiconductor device of claim 12,
further comprising a plurality of additional heterogeneous device stacks, the plurality of additional heterogeneous devices stacks having four sides and further comprising:
a plurality of layers of the first layer type and a plurality of layers of the second layer type, wherein a first side of the fours sides has a plurality of stepped surfaces and defines the first average sidewall angle.

### Claim 17 (depends on 12)

The multilayer semiconductor device of claim 12, wherein the first layer type comprises silicon and the second layer type comprises an insulator.

### Claim 18 (depends on 12)

The multilayer semiconductor device of claim 12, further comprising a first electrical contact formed on a first layer of the first layer type and a second electrical contact formed on a second layer of the first layer type, the second layer being spaced from the first layer by one layer of the second layer type.