# US 9,520,358 B2 · Via structure for optimizing signal porosity

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- Number: US 9,520,358 B2
- Document ID: US9520358B2
- Status: Granted
- Kind: B2
- Application number: 14/744,634
- Filed: 2015-06-19
- Published: 2016-05-05
- Granted: 2016-12-13
- Earliest claimed: 2014-10-30
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Xiongfei Meng; Joon Hyung Chung; Yuancheng Christopher Pan
- Web page: https://patentgrep.com/patent/US9520358B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.

## Claims

### Claim 1

An apparatus including a conductive stack structure, comprising:
a metal x (Mx) layer interconnect on an Mx layer and extending in a first direction on a first track;
a metal y (My) layer interconnect on an My layer, the My layer being a lower layer than the Mx layer;
a first via stack coupled between the Mx layer interconnect and the My layer interconnect, the first via stack including a first metal x−1 (Mx-1) layer interconnect on an Mx-1 layer and including a plurality of vias, the first Mx-1 layer interconnect being a higher layer than the My layer interconnect, the first Mx-1 layer interconnect extending in a second direction on a second track, the second direction being orthogonal to the first direction, the plurality of vias including a first via connected to the Mx layer interconnect and the first Mx-1 layer interconnect within an overlapping portion of the first track and the second track, the plurality of vias including a second via coupled between the My layer interconnect and the first Mx-1 layer interconnect, the second via being within an overlapping portion of the first track and the second track;
a second via stack coupled between the Mx layer interconnect and the My layer interconnect, the second via stack including a second Mx-1 layer interconnect and a second plurality of vias, the second Mx-1 layer interconnect extending in the second direction on a third track, the second plurality of vias including a third via connected to the Mx layer interconnect and the second Mx-1 layer interconnect within an overlapping portion of the first track and the third track, the second plurality of vias including a fourth via coupled between the My layer interconnect and the second Mx-1 layer interconnect, the fourth via being within an overlapping portion of the first track and the third track;
a second Mx layer interconnect extending in the first direction on a fourth track immediately adjacent to the first track; and
a third Mx layer interconnect extending in the first direction on a fifth track immediately adjacent to the first track, the Mx layer interconnect being between the second Mx layer interconnect and the third Mx layer interconnect, the second Mx layer interconnect and the third Mx layer interconnect being uncoupled to each other.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein:
the first via and the second via each have a width of approximately w, and the first Mx-1 layer interconnect extends past the first via and the second via by at least a length 3w; and
the third via and the fourth via each have a width of approximately w, and the second Mx-1 layer interconnect extends past the third via and the fourth via by at least a length 3w.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a third Mx-1 layer interconnect extending in the second direction between the first Mx-1 layer interconnect and the second Mx-1 layer interconnect, the third Mx-1 layer interconnect being uncoupled to the first Mx-1 layer interconnect and the second Mx-1 layer interconnect.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the Mx layer interconnect is uncoupled to any interconnect on the Mx layer.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first Mx-1 layer interconnect is uncoupled to any interconnect on the Mx-1 layer other than the second Mx-1 layer interconnect.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the first Mx-1 layer interconnect is uncoupled to any via between the Mx layer and the Mx-1 layer except for the first via.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the second Mx-1 layer interconnect is uncoupled to any interconnect on the Mx-1 layer other than the first Mx-1 layer interconnect.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the second Mx-1 layer interconnect is uncoupled to any via between the Mx layer and the Mx-1 layer except for the third via.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the My layer is an M3 layer.

### Claim 10 (depends on 1)

The apparatus of claim 1, further comprising a plurality of metal oxide semiconductor (MOS) transistors located below the My layer interconnect, wherein the My layer interconnect is coupled to a source of at least one of the plurality of MOS transistors.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the first and third vias are separated by at least one track, and the second and fourth vias are separated by at least one track.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the first and third vias are separated by one track, and the second and fourth vias are separated by one track.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the first Mx-1 layer interconnect extends across at least three tracks.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the first and second via stacks provide one of power or ground from the Mx layer interconnect to the My layer interconnect.