# US 9,520,351 B2 · Packaging substrate and package structure

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- Number: US 9,520,351 B2
- Document ID: US9520351B2
- Status: Granted
- Kind: B2
- Application number: 14/564,145
- Filed: 2014-12-09
- Published: 2015-11-19
- Granted: 2016-12-13
- Earliest claimed: 2014-05-19
- Assignees: Siliconware Precision Industries Co., Ltd.
- Applicants: Siliconware Precision Industries Co., Ltd.
- Inventors: Chang-Fu Lin; Chin-Tsai Yao; Ming-Chin Chuang; Ko-Cheng Liu; Fu-Tang Huang
- Web page: https://patentgrep.com/patent/US9520351B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H05K 1/0298: {Multilayer circuits}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage}
- H05K 2201/0191: wherein the thickness of the dielectric plays an important role
- H05K 2201/0195: Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
- H10W 70/655: Fan-out layouts
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.

## Claims

### Claim 1

A packaging substrate having a first surface and a second surface opposing the first surface, wherein the first surface is a chip mounting side, and the second surface is a non-chip mounting side, comprising: a core layer; a plurality of dielectric layers, at least two of which having a difference in thickness, wherein one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and the dielectric layers are symmetrically distributed on two opposing surfaces of the core layer with the core layer as a center; and a plurality of circuit layers alternately stacked with the dielectric layers.

### Claim 2 (depends on 1)

The packaging substrate of claim 1, wherein the dielectric layers are reduced progressively in thickness from the first surface to the second surface.

### Claim 3 (depends on 1)

The packaging substrate of claim 1, wherein one half of the dielectric layers that are close to the first surface have a thickness sum greater than a thickness sum of the other half of the dielectric layers that are close to the second surface.

### Claim 4 (depends on 1)

The packaging substrate of claim 1, wherein a thickness ratio between a thickest one of the dielectric layers and a thinnest one of the dielectric layers is 1.2:1 to 2:1.

### Claim 5 (depends on 4)

The packaging substrate of claim 4, wherein a thickness ratio between the thickness one and the thinnest one is 1.5:1.

### Claim 6 (depends on 1)

The packaging substrate of claim 1, wherein the thickest dielectric layer and the thinnest dielectric layer have a thickness difference of 10 to 50 μm.

### Claim 7 (depends on 6)

The packaging substrate of claim 6, wherein the thickest dielectric layer and the thinnest dielectric layer have a thickness difference of 10 to 25 μm.

### Claim 8 (depends on 1)

The packaging substrate of claim 1, wherein the number of the dielectric layers is an even or odd number.

### Claim 9

A packaging substrate having a first surface and a second surface opposing the first surface, wherein the first surface is a chip mounting side, and the second surface is a non-chip mounting side, comprising: a plurality of dielectric layers, at least two of which having a difference in thickness, wherein one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and wherein one of the dielectric layers that is closest to the first surface in position has a thickness greater than each of thicknesses of the others of the dielectric layers, and one of the dielectric layers that is closest to the second surface in position has a thickness less than each of thicknesses of the others of the dielectric layers; and a plurality of circuit layers alternately stacked with the dielectric layers.

### Claim 10 (depends on 9)

The packaging substrate of claim 9, wherein the dielectric layers, except the one that is closest to the first surface and the one that is closest to the second surface in position, have the same thickness.

### Claim 11 (depends on 9)

The packaging substrate of claim 9, wherein a core layer is disposed therebetween, and the dielectric layers are symmetrically distributed on two opposing surfaces of the core layer with the core layer as a center.

### Claim 12 (depends on 9)

The packaging substrate of claim 9, wherein the dielectric layers are reduced progressively in thickness from the first surface to the second surface.

### Claim 13 (depends on 9)

The packaging substrate of claim 9, wherein one half of the dielectric layers that are close to the first surface have a thickness sum greater than a thickness sum of the other half of the dielectric layers that are close to the second surface.

### Claim 14 (depends on 9)

The packaging substrate of claim 9, wherein a thickness ratio between a thickest one of the dielectric layers and a thinnest one of the dielectric layers is 1.2:1 to 2:1.

### Claim 15 (depends on 14)

The packaging substrate of claim 14, wherein a thickness ratio between the thickness one and the thinnest one is 1.5:1.

### Claim 16 (depends on 9)

The packaging substrate of claim 9, wherein the thickest dielectric layer and the thinnest dielectric layer have a thickness difference of 10 to 50 μm.

### Claim 17 (depends on 16)

The packaging substrate of claim 16, wherein the thickest dielectric layer and the thinnest dielectric layer have a thickness difference of 10 to 25 μm.

### Claim 18 (depends on 9)

The packaging substrate of claim 9, wherein the number of the dielectric layers is an even or odd number.

### Claim 19

A package structure, comprising:
a packaging substrate having a first surface, a second surface opposing the first surface, a core layer, a plurality of dielectric layers, and a plurality of circuit layers alternately stacked with the dielectric layers, wherein at least two of the dielectric layers have a difference in thickness, one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and the dielectric layers are symmetrically distributed on two opposing surfaces of the core layer with the core layer as a center; and
a chip mounted on a first surface of the packaging substrate.

### Claim 20 (depends on 19)

The package structure of claim 19, wherein the number of the dielectric layers is even or odd.

### Claim 21

A package structure, comprising:
a packaging substrate having a first surface, a second surface opposing the first surface, a core layer, a plurality of dielectric layers, and a plurality of circuit layers alternately stacked with the dielectric layers, wherein at least two of the dielectric layers have a difference in thickness, one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and wherein one of the dielectric layers that is closest to the first surface in position has a thickness greater than each of thicknesses of the others of the dielectric layers, and one of the dielectric layers that is closest to the second surface in position has a thickness less than each of thicknesses of the others of the dielectric layers; and
a chip mounted on a first surface of the packaging substrate.

### Claim 22 (depends on 21)

The package structure of claim 21, wherein the dielectric layers, except the one that is closest to the first surface and the one that is closest to the second surface, have the same thickness.

### Claim 23 (depends on 19)

The package structure of claim 19, wherein the thicknesses of the dielectric layers are progressively reduced from the first surface to the second surface.

### Claim 24 (depends on 19)

The package structure of claim 19, wherein one half of the dielectric layers that are close to the first surface in position have a thickness sum greater than a thickness sum of the other half of the dielectric layers that are close to the second surface in position.

### Claim 25 (depends on 19)

The package structure of claim 19, wherein a thickness ratio between a thickest one of the dielectric layers and a thinnest one of the dielectric layers is 1.2:1 to 2:1.

### Claim 26 (depends on 25)

The package structure of claim 25, wherein a thickness ratio between the thickness one and the thinnest one is 1.5:1.

### Claim 27 (depends on 19)

The package structure of claim 19, wherein a thickest one of the dielectric layers is thicker than a thinnest one of the dielectric layers by 10 to 50 μm.

### Claim 28 (depends on 27)

The package structure of claim 27, wherein the thickest one is thicker than the thinnest one by 10 to 25 μm.

### Claim 29 (depends on 21)

The package structure of claim 21, wherein a core layer is disposed therebetween, and the dielectric layers are symmetrically distributed on two opposing surfaces of the core layer by taking the core layer as a center.

### Claim 30 (depends on 21)

The packaging substrate of claim 21, wherein the thicknesses of the dielectric layers are reduced progressively from the first surface to the second surface.

### Claim 31 (depends on 21)

The packaging substrate of claim 21, wherein one half of the dielectric layers that are close to the first surface have a thickness sum greater than a thickness sum of the other half of the dielectric layers that are close to the second surface.

### Claim 32 (depends on 21)

The packaging substrate of claim 21, wherein a thickness ratio between a thickest one of the dielectric layers and a thinnest one of the dielectric layers is 1.2:1 to 2:1.

### Claim 33 (depends on 32)

The packaging substrate of claim 32, wherein a thickness ratio between the thickness one and the thinnest one is 1.5:1.

### Claim 34 (depends on 21)

The packaging substrate of claim 21, wherein the thickest dielectric layer and the thinnest dielectric layer have a thickness difference of 10 to 50 μm.

### Claim 35 (depends on 34)

The packaging substrate of claim 34, wherein the thickest dielectric layer and the thinnest dielectric layer have a thickness difference of 10 to 25 μm.

### Claim 36 (depends on 21)

The packaging substrate of claim 21, wherein the number of the dielectric layers is an even or odd number.