# US 9,520,350 B2 · Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer

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- Number: US 9,520,350 B2
- Document ID: US9520350B2
- Status: Granted
- Kind: B2
- Application number: 13/801,859
- Filed: 2013-03-13
- Published: 2014-09-18
- Granted: 2016-12-13
- Earliest claimed: 2013-03-13
- Assignees: Intel Corporation
- Applicants: Weng Hong Teh; Emile Davies-Venn; Ebrahim Andideh; Digvijay A. Raorane; Daniel N. Sobieski
- Inventors: Weng Hong Teh; Emile Davies-Venn; Ebrahim Andideh; Digvijay A. Raorane; Daniel N. Sobieski
- Web page: https://patentgrep.com/patent/US9520350B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W 20/084: {for dual-damascene structures}
- H10W 20/086: {involving buried masks}
- H10W 20/0884: {involving forming vias by burying sacrificial pillars in the dielectric parts and removing the pillars}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

## Claims

### Claim 1

A semiconductor package, comprising:
a layer comprising a pattern of spaced apart conductive lines;
a first dielectric layer disposed on and between the conductive lines of the pattern of spaced apart conductive lines;
a second dielectric layer disposed above the first dielectric layer;
a conductive via disposed in the first dielectric layer;
a conductive routing line disposed in the second dielectric layer and coupled to the conductive via; and
a patterned titanium nitride layer disposed directly between the first and second dielectric layers, wherein the conductive via is disposed in the patterned titanium nitride layer, and the conductive routing line is disposed on the patterned titanium nitride layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the first and second dielectric layers are substrate dielectric build-up layers.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the first and second dielectric layers are non-photo-definable substrate dielectric build-up layers.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein the first dielectric layer is a non-photo-definable substrate dielectric build-up layer, and the second dielectric layer is a photo-definable substrate dielectric build-up layer.

### Claim 5 (depends on 2)

The semiconductor package of claim 2, wherein the first dielectric layer is a photo-definable substrate dielectric build-up layer, and the second dielectric layer is a non-photo-definable substrate dielectric build-up layer.

### Claim 6 (depends on 2)

The semiconductor package of claim 2, wherein the first and second dielectric layers are photo-definable substrate dielectric build-up layers.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, further comprising:
a silicon nitride layer disposed on the conductive routing line and on exposed portions of the second dielectric layer.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the pattern of spaced apart conductive lines has a fine line spacing (FLS) of less than 8 micron/8 micron FLS.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the pattern of spaced apart conductive lines, the conductive via, and the conductive routing line all comprise copper.

### Claim 10

An apparatus, comprising:
a semiconductor die comprising an integrated circuit having a plurality of external electrical contacts; and
a semiconductor package housing the semiconductor die, the semiconductor package comprising:
a layer comprising a pattern of spaced apart conductive lines coupled to the plurality of external contacts of the semiconductor die;
a first dielectric layer disposed on and between the conductive lines of the pattern of spaced apart conductive lines;
a second dielectric layer disposed above the first dielectric layer;
a conductive via disposed in the first dielectric layer;
a conductive routing line disposed in the second dielectric layer and coupled to the conductive via; and
a patterned titanium nitride layer disposed directly between the first and second dielectric layers, wherein the conductive via is disposed in the patterned titanium nitride layer, and the conductive routing line is disposed on the patterned titanium nitride layer.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the plurality of external electrical contacts is a plurality of external bumps.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the first and second dielectric layers of the semiconductor package are substrate dielectric build-up layers.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein one or both of the first and second dielectric layers is a photo-definable substrate dielectric build-up layer.

### Claim 14 (depends on 10)

The apparatus of claim 10, the semiconductor package further comprising:
a second silicon nitride layer disposed on the conductive routing line and on exposed portions of the second dielectric layer.

### Claim 15 (depends on 10)

The apparatus of claim 10, wherein the pattern of spaced apart conductive lines of the semiconductor package has a fine line spacing (FLS) of less than 8 micron/8 micron FLS.