# US 9,520,349 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,349 B2 - Document ID: US9520349B2 - Status: Granted - Kind: B2 - Application number: 14/611,354 - Filed: 2015-02-02 - Published: 2015-05-28 - Granted: 2016-12-13 - Earliest claimed: 2012-03-27 - Assignees: Mediatek Inc. - Applicants: MediaTek Inc. - Inventors: Wen-Sung Hsu; Tzu-Hung Lin; Ta-Jen Yu - Web page: https://patentgrep.com/patent/US9520349B2 ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 74/134: {the encapsulations being in grooves in the semiconductor body} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 74/147: {the encapsulations being multilayered} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/072: {of bump connectors} - H10W 72/07254: {changes in dispositions} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/30: Die-attach connectors - H10W 72/354: {comprising polymers} - H10W 72/387: {Flow barriers} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. A conductive trace is disposed on the substrate. A conductive pillar bump is disposed on the conductive trace, wherein the conductive bump is coupled to a die. In another configuration, a first conductive trace is disposed on the substrate, and a second conductive trace is disposed on the substrate. In the second configuration, a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die. A first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate, and a die is disposed over the first conductive trace. ## Claims ### Claim 1 A semiconductor package, comprising: a substrate; a conductive trace disposed on the substrate; a conductive pillar bump disposed on the conductive trace, wherein the conductive pillar bump is coupled to a die; and a solder resistance layer disposed on the substrate, wherein an extending portion of the solder resistance layer extends along the conductive trace into an overlapping region between the die and the substrate. ### Claim 2 (depends on 1) The semiconductor package as claimed in claim 1, wherein the conductive trace comprises a first portion having a first width and a second portion having a second width, and the conductive pillar bump is disposed on the second portion of the conductive trace. ### Claim 3 (depends on 2) The semiconductor package as claimed in claim 2, wherein the semiconductor package comprises a plurality of conductive pillar bumps disposed on the second portion of the conductive trace. ### Claim 4 (depends on 1) The semiconductor package as claimed in claim 1, wherein the semiconductor package further comprises a metal pad located between the conductive trace and the substrate. ### Claim 5 (depends on 1) The semiconductor package as claimed in claim 1, wherein the semiconductor package further comprises a metal pad located between the conductive pillar bump and the conductive trace. ### Claim 6 (depends on 1) The semiconductor package as claimed in claim 1, wherein the conductive trace comprises a plurality of conductive layers and a metal pad, wherein the metal pad is sandwiched by the plurality of conductive layers. ### Claim 7 (depends on 1) The semiconductor package as claimed in claim 1, wherein the extending portion of the solder resistance layer covers a portion of the conductive trace, and a width of the extending portion of the solder resistance layer is larger than that of the portion of the conductive trace. ### Claim 8 (depends on 1) The semiconductor package as claimed in claim 1, wherein the extending portion of the solder resistance layer covers a portion of the conductive trace, and the extending portion of the solder resistance layer and the portion of the conductive trace collectively have a T-shaped cross section. ### Claim 9 (depends on 1) The semiconductor package as claimed in claim 1, wherein the solder resistance layer further has a second extending portion, and the conductive pillar bump is positioned between the extending portion and the second extending portion. ### Claim 10 (depends on 1) The semiconductor package as claimed in claim 1, wherein the extending portion is separated from the substrate. ### Claim 11 (depends on 1) The semiconductor package as claimed in claim 1, further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is sandwiched by the extending portion and the die. ### Claim 12 (depends on 1) The semiconductor package as claimed in claim 1, further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is sandwiched by the extending portion and the substrate. ### Claim 13 (depends on 1) The semiconductor package as claimed in claim 1, further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is in direct contact with the substrate. ### Claim 14 A semiconductor package, comprising: a substrate; a conductive trace disposed on the substrate; a conductive pillar bump disposed on the conductive trace, wherein the conductive pillar bump is coupled to a die; and a solder resistance layer, wherein a portion of the solder resistance layer and a portion of the conductive trace collectively have a T-shaped cross section, wherein the portion of the solder resistance layer forms a top, horizontal portion of the T-shape, and the portion of the first conductive trace forms a lower, vertical portion of the T-shape that contacts the top, horizontal portion at a substantial midpoint of the top horizontal portion. ### Claim 15 (depends on 14) The semiconductor package as claimed in claim 14, wherein a width of the portion of the solder resistance layer is larger than that of the portion of the conductive trace. ### Claim 16 (depends on 14) The semiconductor package as claimed in claim 14, wherein the portion of the solder resistance layer is separated from the substrate. ### Claim 17 (depends on 14) The semiconductor package as claimed in claim 14, further comprising an underfill material between the substrate and the die, wherein a portion of the underfill material is in direct contact with the substrate. ### Claim 18 (depends on 14) The semiconductor package as claimed in claim 14, further comprising an underfill material between the substrate and the die, wherein the portion of the solder resistance layer is embedded in the underfill material. ### Claim 19 (depends on 14) The semiconductor package as claimed in claim 14, wherein a bottom surface of the portion of the solder resistance layer faces the conductive trace, and a portion of the bottom surface is exposed from the portion of the conductive trace. ### Claim 20 (depends on 19) The semiconductor package as claimed in claim 19, further comprising an underfill material between the substrate and the die, wherein the portion of the bottom surface is wrapped by the underfill material.