# US 9,520,348 B2 · Semiconductor devices and methods of manufacturing the same

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- Number: US 9,520,348 B2
- Document ID: US9520348B2
- Status: Granted
- Kind: B2
- Application number: 13/803,935
- Filed: 2013-03-14
- Published: 2013-11-07
- Granted: 2016-12-13
- Earliest claimed: 2012-05-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Byoungdeog Choi; JungWoo Seo; Sangyeon Han; Hyun-Woo Chung; Hongrae Kim; Yoosang Hwang
- Inventors: Byoungdeog Choi; JungWoo Seo; Sangyeon Han; Hyun-Woo Chung; Hongrae Kim; Yoosang Hwang
- Web page: https://patentgrep.com/patent/US9520348B2

## CPC

- H10W 20/46: comprising air gaps
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/8825: {Selenides, e.g. GeSe}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/48: Insulating materials thereof
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.

## Claims

### Claim 1

A semiconductor device, comprising:
a pair of line patterns disposed on a substrate;
a contact plug disposed between the pair of line patterns;
an air gap disposed between the contact plug and the line patterns;
a landing pad extending from a top end of the contact plug to cover a first part of the air gap; and
an insulating layer disposed on a second part of the air gap, which is not covered by the landing pad;
wherein each of the pair of line patterns comprises a conductive wire and a hard mask pattern sequentially stacked on the substrate, the hard mask pattern comprising an insulating material, and
wherein the landing pad is contact with a top surface of the hard mask pattern of a line pattern adjacent to the first part of the air gap.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a height of the first part of the air gap covered by the landing pad is greater than a height of the second part of the air gap not covered by the landing pad.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first protecting spacer disposed between the line pattern and the contact plug; and
a second protecting spacer disposed between the contact plug and the first protecting spacer,
wherein the air gap is disposed between the first protecting spacer and the second protecting spacer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein top ends of the first and second protecting spacers under the landing pad are in contact with each other, so that a top end of the first part of the air gap is closed by the top ends of the first and second protecting spacers under the landing pad.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein a top end of the first part of the air gap is closed by the landing pad.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a pair of insulating fences disposed between the pair of line patterns,
wherein the contact plug is disposed between the pair of line patterns and between the pair of insulating fences; and
wherein a bottom surface of the contact plug has a quadrangular shape in a plan view.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a selection component under the line patterns on the substrate; and
a data storage part electrically connected to a top surface of the landing pad,
wherein each of the line patterns includes a conductive wire;
wherein the conductive wire of one of the pair of line patterns is electrically connected to a first terminal of the selection component; and
wherein the data storage part is electrically connected to a second terminal of the selection component through the landing pad and the contact plug.

### Claim 8

A semiconductor device, comprising:
a pair of line patterns disposed on a substrate;
a contact plug disposed between the pair of line patterns;
an air gap disposed between the contact plug and the line patterns;
a landing pad extending from a top end of the contact plug to cover a first part of the air gap; and
an insulating layer disposed on the landing pad and a second part of the air gap, which is not covered by the landing pad;
wherein the air gap has a closed loop-shape surrounding the contact plug in a plan view.

### Claim 9

A semiconductor device, comprising:
a pair of line patterns disposed on a substrate;
a contact plug disposed between the pair of line patterns; and
a spacer structure disposed between the contact plug and each of the line patterns,
wherein the spacer structure comprises:
a first protecting spacer adjacent to each of the line patterns;
a second protecting spacer adjacent to a sidewall of the contact plug; and
an air gap disposed between the first and second protecting spacers;
wherein the second protecting spacer extends to surround the sidewall of the contact plug and has a closed loop-shape in a plan view;
wherein the air gap extends to surround the sidewall of the contact plug and has a closed loop-shape in a plan view; and
wherein the first protecting spacer has a line-shape extending along a sidewall of each of the line patterns.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
a pair of insulating fences disposed between the pair of line patterns,
wherein the contact plug is disposed between the pair of line patterns and between the pair of insulating fences; and
wherein the extending part of the air gap is disposed between the extending part of the second protecting spacer and each of the insulating fences.