# US 9,520,347 B2 · Lead frame construct for lead-free solder connections

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- Number: US 9,520,347 B2
- Document ID: US9520347B2
- Status: Granted
- Kind: B2
- Application number: 14/888,321
- Filed: 2014-04-22
- Published: 2016-03-03
- Granted: 2016-12-13
- Earliest claimed: 2013-05-03
- Assignees: Honeywell International Inc.
- Applicants: Honeywell International Inc.
- Inventors: Jianxing Li; Kevin B. Albaugh
- Web page: https://patentgrep.com/patent/US9520347B2

## CPC

- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/04: of leadframes
- H10W 70/40: Leadframes
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 72/30: Die-attach connectors
- H10W 72/073: {of die-attach connectors}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07355: {changes in materials}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/3528: {Intermetallic compounds}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 76/17: characterised by their materials
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement.

## Claims

### Claim 1

An electronics packaging arrangement, comprising:
a lead frame having a surface;
a metallic barrier layer disposed on said surface of said lead frame;
a chip connected to said metallic barrier layer via a zinc-based solder layer; and
an intermetallic layer disposed between said metallic barrier layer and said zinc-based solder layer, said intermetallic layer comprising an intermetallic compound including zinc.

### Claim 2 (depends on 1)

The arrangement of claim 1, wherein said intermetallic compound is a zinc-copper intermetallic compound.

### Claim 3 (depends on 1)

The arrangement of claim 1, wherein said intermetallic layer has a thickness between 3 μm and 10 μm.

### Claim 4 (depends on 1)

The arrangement of claim 1, wherein said metallic barrier layer comprises one of nickel and a nickel alloy, and has a thickness between 1 μm and 10 μm.

### Claim 5 (depends on 1)

The arrangement of claim 1, wherein an area of said chip-to-lead frame connection is greater than 25 mm2.

### Claim 6 (depends on 1)

The arrangement of claim 1, wherein the intermetallic layer comprises at least one member selected from the group consisting of copper and a copper alloy.

### Claim 7 (depends on 1)

The arrangement of claim 1, wherein the intermetallic layer comprises at least one member selected from the group consisting of zinc, bismuth, tin, indium, gold, silver, palladium, platinum and alloys thereof.

### Claim 8

A method of manufacturing an electronics packaging arrangement, said method comprising the steps of:
providing a lead frame including a metallic barrier layer disposed on a surface of the lead frame, and a wetting promoting layer disposed on the metallic barrier layer;
connecting a chip to the lead frame by the following steps:
flowing a zinc-based solder over the wetting promoting layer;
placing a chip on the zinc-based solder; and
solidifying the zinc-based solder with formation of an intermetallic layer between the zinc-based solder and the metallic barrier layer, the intermetallic layer comprising an intermetallic compound including zinc.

### Claim 9 (depends on 8)

The method of claim 8, wherein the wetting promoting layer is selected from copper and a copper alloy, and the intermetallic compound is a zinc-copper intermetallic compound.

### Claim 10 (depends on 8)

The method of claim 8, wherein the wetting promoting layer is selected from zinc, bismuth, tin, indium, gold, silver, palladium, platinum and alloys thereof, and the intermetallic compound is a zinc-copper intermetallic compound.

### Claim 11 (depends on 8)

The method of claim 8, wherein the intermetallic layer comprises copper or copper alloy.

### Claim 12 (depends on 8)

The method of claim 8, wherein said solidifying step further comprises forming the intermetallic layer to a thickness between 3 μm and 10 μm.

### Claim 13 (depends on 8)

The method of claim 8, wherein said metallic barrier layer comprises one of nickel and a nickel alloy, and has a thickness between 1 μm and 10 μm.

### Claim 14 (depends on 8)

The method of claim 8, wherein an area of the chip-to-lead frame connection is greater than 25 mm2.