# US 9,520,342 B2 · Power management applications of interconnect substrates

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,342 B2
- Document ID: US9520342B2
- Status: Granted
- Kind: B2
- Application number: 14/753,305
- Filed: 2015-06-29
- Published: 2015-10-22
- Granted: 2016-12-13
- Earliest claimed: 2011-10-07
- Assignees: Volterra Semiconductor Corporation
- Applicants: Volterra Semiconductor Corporation
- Inventors: Mihalis Michael; Kwang Hong Tan; Ilija Jergovic; Chiteh Chiang; Anthony Stratakos
- Web page: https://patentgrep.com/patent/US9520342B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 20/427: {Power or ground buses}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 40/10: Arrangements for heating
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/461: {specially adapted for cooling}
- H10W 70/465: {Bumps or wires}
- H10W 70/467: {Multilayered additional interconnections}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/635: {Through-vias}
- H10W 70/66: Conductive materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Various applications of interconnect substrates in power management systems are described.

## Claims

### Claim 1

A package, comprising:
a device including one or more power devices configured as part of a switching regulator, the switching regulator having a power node terminal and a switching terminal; and
a premolded interconnect substrate for connecting the device to an assembly, the premolded interconnect substrate including a plurality of electrically conductive structures, a first subset of the electrically conductive structures corresponding to the power node terminal, a second subset of the electrically conductive structures corresponding to the switching terminal;
wherein the device is mounted on exposed portions of the electrically conductive structures adjacent a first surface of the interconnect substrate via conductive bumps thereby connecting the first subset of the electrically conductive structures to the power node terminal and the second subset of the electrically conductive structures to the switching terminal, and wherein exposed portions of the first and second subsets of the electrically conductive structures at a second surface of the interconnect substrate that is opposite the first surface of the interconnect substrate are configured for connection to first and second conductive planes of the assembly, respectively, such that connections between the first subset of electrically conductive structures and the first conductive plane are made along a portion of the second surface of the interconnect substrate proximate a first edge of the interconnect substrate, and connections between the second subset of electrically conductive structures and the second conductive plane are made along a second portion of the second surface proximate a second edge of the interconnect substrate opposing the first edge.

### Claim 2 (depends on 1)

The package of claim 1 wherein the one or more power devices comprise two power devices, and wherein the switching regulator includes two power node terminals and the switching terminal.

### Claim 3 (depends on 1)

The package of claim 1 wherein at least one of the electrically conductive structures is enclosed in the interconnect substrate by at least one other of the electrically conductive structures.

### Claim 4 (depends on 1)

The package of claim 1 wherein the device includes control circuitry associated with the one or more power devices, and wherein some of the electrically conductive structures correspond to control circuit nodes of the control circuitry.

### Claim 5 (depends on 1)

The package of claim 1 wherein at least some of the electrically conductive structures of the interconnect substrate have discrete passive circuit elements connected thereto.

### Claim 6 (depends on 5)

The package of claim 5 wherein the discrete passive circuit elements include a plurality of capacitors connected to the terminals of the switching regulator.

### Claim 7 (depends on 6)

The package of claim 6 wherein the power node terminal or the switching terminal has two or more of the plurality of capacitors connected thereto, the two or more capacitors being mounted on the interconnect substrate along more than one edge of the device.

### Claim 8 (depends on 6)

The package of claim 6 wherein one or more of the capacitors corresponding to the power node terminal are mounted along the second edge of the interconnect substrate.

### Claim 9 (depends on 5)

The package of claim 5 wherein the electrically conductive structures to which a first one of the discrete passive elements is connected are configured for indirect connection to the assembly via internal routing of the interconnect substrate.

### Claim 10 (depends on 5)

The package of claim 5 wherein one or more of the discrete passive circuit elements are mounted on the interconnect substrate between adjacent ones of the conductive bumps.

### Claim 11 (depends on 1)

The package of claim 1 further comprising an underfill material occupying space between the conductive bumps connecting the electrically conductive structures of the interconnect substrate to the device.

### Claim 12 (depends on 11)

The package of claim 11 wherein the underfill material comprises either a dispensed underfill or a molded underfill.

### Claim 13 (depends on 11)

The package of claim 11 wherein the underfill material is part of an encapsulation material at least partially encapsulating the device.

### Claim 14 (depends on 1)

The package of claim 1 wherein the device is mounted on the electrically conductive structures of the interconnect substrate on a first side of the device, and wherein a second side of the device opposing the first side is exposed for heat removal.

### Claim 15 (depends on 14)

The package of claim 14 wherein the interconnect substrate includes a thermally conductive structure, the package further comprising a heat spreader structure mounted on the exposed second side of the device and thermally connected to the thermally conductive structure of the interconnect substrate to promote heat conduction from the device to the thermally conductive structure.

### Claim 16 (depends on 15)

The package of claim 15 wherein at least a portion of the thermally conductive structure extends through the interconnect substrate and is configured for connection to the assembly, thereby enabling conduction of the heat from the device to the assembly.

### Claim 17 (depends on 15)

The package of claim 15 further comprising one or more portions of a carrier frame disposed along one or more edges of the interconnect substrate adjacent the device, the heat spreader structure being thermally connected to the thermally conductive structure of the interconnect substrate via the portions of the carrier frame.

### Claim 18 (depends on 15)

The package of claim 15 wherein the heat spreader structure comprises a plurality of disconnected or partially connected portions, and/or one or more apertures.

### Claim 19 (depends on 1)

The package of claim 1 further comprising:
a second device; and
a second interconnect substrate for connecting the second device to the assembly via the interconnect substrate, the second interconnect substrate including a second plurality of electrically conductive structures;
wherein the second device is mounted on exposed portions of the second plurality of electrically conductive structures via second conductive bumps, and wherein the second interconnect substrate is mounted on the device with at least some of the second plurality of electrically conductive structures being connected to one or more of the plurality of electrically conductive structures of the interconnect substrate via third conductive bumps adjacent an edge of the device.