# US 9,520,341 B2 · Semiconductor package with conductive clips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,341 B2 - Document ID: US9520341B2 - Status: Granted - Kind: B2 - Application number: 14/663,276 - Filed: 2015-03-19 - Published: 2015-07-09 - Granted: 2016-12-13 - Earliest claimed: 2011-01-03 - Assignees: Infineon Technologies Americas Corp. - Applicants: Infineon Technologies Americas Corp. - Inventors: Eung San Cho; Chuan Cheah - Web page: https://patentgrep.com/patent/US9520341B2 ## CPC - H10W 70/464: {Additional interconnections in combination with leadframes} - H10W 70/466: {Tape carriers or flat leads} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 90/00: Package configurations - H10W 90/811: {Multiple chips on leadframes} - H10W 72/07636: {Soldering or alloying} - H10W 72/07637: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07653: {changes in shapes} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/652: {comprising metals or metalloids, e.g. silver} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/753: {between laterally-adjacent chips} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. ## Claims ### Claim 1 A semiconductor package comprising: a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain; a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source and a sync gate; a first conductive clip electrically coupling said control drain to a first pad of said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe; said control gate electrically coupled to a second pad of said leadframe; a driver integrated circuit (IC) disposed on a third pad of said leadframe, said third pad isolated from said common region; a second conductive clip electrically coupling said sync source to a fourth pad of said lead frame, wherein said first pad and said fourth pad are disposed along a common peripheral edge of said leadframe such that said control transistor and said sync transistor are not situated between said first pad and said fourth pad. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein said driver IC is electrically coupled to said sync gate using a wirebond. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein said sync source and said sync gate are arranged into a grid. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein said semiconductor package is a leadless package. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein said first conductive clip is attached to said control drain by solder. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein said semiconductor package comprises a buck converter. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein said first conductive clip comprises a copper clip. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein said sync transistor comprises a III-nitride depletion mode transistor. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein said control transistor comprises a III-nitride depletion mode transistor. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein said control gate is situated on said second pad of said leadframe. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein said driver IC is electrically coupled to said control gate using said second pad of said leadframe. ### Claim 12 A semiconductor package comprising: a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain; a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source; a driver integrated circuit (IC) disposed on said leadframe and configured to drive said control transistor and said sync transistor; a first conductive clip electrically coupling said control drain to a first pad of said leadframe; said control gate electrically coupled to a second pad of said leadframe; said driver IC disposed on a third pad of said leadframe; a second conductive clip electrically coupling said sync source to a fourth pad of said lead frame, wherein said first pad and said fourth pad are disposed along a common peripheral edge of said leadframe such that said control transistor and said sync transistor are not situated between said first pad and said fourth pad. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein said driver IC is electrically coupled to a sync gate on said top surface of said sync transistor using a wirebond. ### Claim 14 (depends on 12) The semiconductor package of claim 12, wherein said sync transistor includes a sync gate arranged into a grid with said sync source on said top surface thereof. ### Claim 15 (depends on 12) The semiconductor package of claim 12, wherein said semiconductor package is a leadless package. ### Claim 16 (depends on 12) The semiconductor package of claim 12, wherein said first conductive clip is attached to said control drain by solder. ### Claim 17 (depends on 12) The semiconductor package of claim 12, wherein said semiconductor package comprises a buck converter. ### Claim 18 (depends on 12) The semiconductor package of claim 12, wherein said first conductive clip comprises a copper clip. ### Claim 19 (depends on 12) The semiconductor package of claim 12, wherein said control transistor comprises a III-nitride depletion mode transistor. ### Claim 20 (depends on 12) The semiconductor package of claim 12, wherein said sync transistor comprises a III-nitride depletion mode transistor.