# US 9,520,340 B2 · Semiconductor die connection system and method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,340 B2
- Document ID: US9520340B2
- Status: Granted
- Kind: B2
- Application number: 14/875,499
- Filed: 2015-10-05
- Published: 2016-01-28
- Granted: 2016-12-13
- Earliest claimed: 2012-01-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Fa Chen; Chen-Hua Yu; Sen-Bor Jan
- Web page: https://patentgrep.com/patent/US9520340B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a first die with a first width having a first side and a second side opposite to the first side;
a through substrate via formed in the first die, wherein an edge of the through substrate via is exposed at the second side of the first die;
a second die with a second width having a first side and a second side, wherein the first side of the second die is bonded to the first side of the first die, and the second width is larger than the first width; and
an encapsulant extending between a sidewall of first die and a surface of the first side of second die.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a redistribution layer in connection with the through substrate via.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a printed circuit board bonded to the first die.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising solder balls located between the first die and the printed circuit board.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first die is a logic die.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the second die is a memory die.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first die and the second die are in a chip on memory architecture.

### Claim 8

A semiconductor device comprising:
a first die with a first width over a second die with a second width, wherein the second width is larger than the first width;
a through substrate via extending through at least a portion of the first die;
an encapsulant extending between a sidewall of the first die and a top surface of the second die; and
a substrate bonded to the first die.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first die is a logic die.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the second die is a memory die.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first width is between about 1 mm and about 25 mm.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the second width is between about 1 mm and about 25 mm.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the first die is bonded to the second die with a copper-copper bond.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the first die and the second die are bonded in a face to face configuration.

### Claim 15

A semiconductor device comprising:
a first die with a first width having a first side and a second side opposite to the first side;
a through substrate via formed in the first die, wherein an edge of the through substrate via is exposed at the second side of the first die;
a second die with a second width having a first side and a second side, wherein the first side of the second die is bonded to the first side of the first die, and the second width is larger than the first width; and
a substrate bonded to the first die.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising a redistribution layer in contact with the through substrate via.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising an external connector in contact with the redistribution layer.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, further comprising a printed circuit board bonded to the first die.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the first die is bonded to the second die with solder balls.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the first die is bonded to the second die with a copper-copper bond.