# US 9,520,339 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 9,520,339 B2
- Document ID: US9520339B2
- Status: Granted
- Kind: B2
- Application number: 14/615,400
- Filed: 2015-02-05
- Published: 2015-06-04
- Granted: 2016-12-13
- Earliest claimed: 2011-10-19
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Akiko Nomachi
- Web page: https://patentgrep.com/patent/US9520339B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/242: {of Group IV materials}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/2125: {Top-view shapes}
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming an insulating layer with an opening on a first surface of a semiconductor substrate;
forming a semiconductor integrated circuit on the first surface of the semiconductor substrate;
forming a conductive layer on the opening, the conductive layer being connected to the semiconductor integrated circuit;
forming a hole extending from a second surface of the semiconductor substrate to the conductive layer through the opening by selectively etching the semiconductor substrate from the second surface of the semiconductor substrate, the hole having a size larger than a size of the opening in a range from the second surface to an interface between the semiconductor substrate and the insulating layer, and having a size equal to the size of the opening in the opening;
forming a via in the hole; and
selectively removing a part of the conductive layer after forming the hole,
wherein the conductive layer comprises a first layer on the insulating layer and a second layer on the first layer, the part of the conductive layer is the first layer, and a size of the conductive layer is smaller than the size of the hole.

### Claim 2 (depends on 1)

The method of claim 1,
wherein the first layer is a conductive polysilicon layer, and the second layer is a metal silicide layer.

### Claim 3 (depends on 1)

The method of claim 1,
wherein a condition of etching the semiconductor substrate is constant from a start of the etching to a time in which the hole reaches to the conductive layer.

### Claim 4 (depends on 1)

The method of claim 1,
wherein a condition of etching the semiconductor substrate is changed before a time in which the hole reaches to the conductive layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming the insulating layer in parallel with forming an element isolation insulating layer which isolates elements in the semiconductor integrated circuit.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming the insulating layer and the conductive layer in an island manner.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming the conductive layer on the insulating layer in a line manner.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming the insulating layer in a ring manner.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming the opening in a circle or square manner.

### Claim 10

A method of manufacturing a semiconductor device, the method comprising:
embedding an insulating layer in a first surface of a semiconductor substrate such that a bottom surface of the insulating layer is lower than the first surface, the insulating layer having a shape of a ring, the ring having an opening inside the ring;
forming a semiconductor integrated circuit on the first surface of the semiconductor substrate;
forming a conductive layer on the semiconductor substrate inside the ring of the insulating layer, the conductive layer being connected to the semiconductor integrated circuit;
forming a hole extending from a second surface of the semiconductor substrate to the bottom surface of the insulating layer and to the first surface of the semiconductor substrate inside the ring, by selectively etching the semiconductor substrate from the second surface of the semiconductor substrate, the hole having a size larger than a size of the opening in a range from the second surface to the bottom surface of the insulating layer, and having a size equal to the size of the opening in the opening;
forming a via in the hole; and
selectively removing a part of the conductive layer after forming the hole,
wherein the conductive layer comprises a first layer and a second layer on the first layer, the part of the conductive layer is the first layer, and a size of the conductive layer is smaller than the size of the hole.

### Claim 11 (depends on 10)

The method of claim 10,
wherein the first layer is a conductive polysilicon layer, and the second layer is a metal silicide layer.

### Claim 12 (depends on 10)

The method of claim 10,
wherein a condition of etching the semiconductor substrate is constant from a start of the etching to a time in which the hole reaches to the conductive layer.

### Claim 13 (depends on 10)

The method of claim 10,
wherein a condition of etching the semiconductor substrate is changed before a time in which the hole reaches to the conductive layer.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
forming the insulating layer in parallel with forming an element isolation insulating layer which isolates elements in the semiconductor integrated circuit.