# US 9,520,333 B1 · Wafer level package and fabrication method thereof

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- Number: US 9,520,333 B1
- Document ID: US9520333B1
- Status: Granted
- Kind: B1
- Application number: 14/745,473
- Filed: 2015-06-22
- Published: 2016-12-22
- Granted: 2016-12-13
- Earliest claimed: 2015-06-22
- Assignees: Inotera Memories, Inc.
- Applicants: Inotera Memories, Inc.
- Inventors: Shing-Yih Shih; Neng-Tai Shih; Hsu Chiang
- Web page: https://patentgrep.com/patent/US9520333B1

## CPC

- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H05K 1/181: associated with surface mounted components
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/69: Insulating materials thereof
- H10W 70/692: Ceramics or glasses
- H10W 74/014: {using batch processing}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor device includes an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side; at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer; a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and a plurality of solder bumps mounted on the first passivation layer on the second side.

## Claims

### Claim 1

A semiconductor device, comprising:
an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side;
at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer;
a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and
a plurality of solder bumps mounted on the first passivation layer on the second side.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first passivation layer comprises silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second passivation layer comprises silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the RDL further comprises a first interlayer dielectric between the first passivation layer and the second passivation layer, a first dielectric block layer between the first interlayer dielectric and the second passivation layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the first interlayer dielectric comprises silicon oxide, BSG, or BPSG.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, wherein the first dielectric block layer comprises silicon nitride.

### Claim 7 (depends on 4)

The semiconductor device according to claim 4, wherein a first metal layer is embedded in the first interlayer dielectric.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the RDL further comprises a second interlayer dielectric between the first passivation layer and first interlayer dielectric, a second dielectric block layer between the first interlayer dielectric and the second interlayer dielectric.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the second interlayer dielectric comprises silicon oxide, BSG, or BPSG.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein the second dielectric block layer comprises silicon nitride.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8, wherein the RDL further comprises a second metal layer and a first via in the second interlayer dielectric, wherein the second metal layer is electrically connected to the first metal layer through the first via.

### Claim 12 (depends on 8)

The semiconductor device according to claim 8, wherein the RDL further comprises a third dielectric block layer between the second interlayer dielectric and the first passivation layer.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the third dielectric block layer comprises silicon nitride.