# US 9,520,331 B2 · Adaptive patterning for panelized packaging

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- Number: US 9,520,331 B2
- Document ID: US9520331B2
- Status: Granted
- Kind: B2
- Application number: 13/891,663
- Filed: 2013-05-10
- Published: 2013-09-19
- Granted: 2016-12-13
- Earliest claimed: 2010-02-16
- Assignees: DECA Technologies Inc.
- Applicants: DECA Technologies Inc.
- Inventors: Christopher M. Scanlan; Timothy L. Olson
- Web page: https://patentgrep.com/patent/US9520331B2

## CPC

- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/00: Interconnections or connectors in packages
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W 46/601: {for use after dicing}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- Y02P 80/30: Reducing waste in manufacturing processes; Calculations of released waste quantities
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

## Claims

### Claim 1

A device package comprising:
a semiconductor die unit that further comprises an outline misaligned with a device package outline;
an encapsulant overmolding the semiconductor die unit;
a build-up structure disposed over both the semiconductor die unit and the encapsulant, the build-up structure comprising:
a redistribution layer (RDL) comprising a first portion aligned with the semiconductor die unit and a second portion formed as an underbump metallization (UBM) via capture pad aligned with the semiconductor die unit, wherein the first portion of the RDL is vertically offset from the semiconductor die unit,
a first via aligned with a bond pad of the semiconductor die unit and disposed between the bond pad and the first portion of the RDL, and
a UBM pad aligned with the device package outline, wherein the UBM via capture pad is disposed over the UBM pad, and
a UBM via aligned with the semiconductor die unit, wherein the UBM via is disposed between the UBM pad and the UBM via capture pad so that at least a portion of the UBM via capture pad and the UBM pad are vertically offset and connected through the UBM via; and
an input/output (I/O) interconnect disposed over the UBM pad, wherein the I/O interconnect is aligned with the device package outline.

### Claim 2 (depends on 1)

The device package of claim 1, wherein the UBM via capture pad is not aligned with the device package outline.

### Claim 3 (depends on 1)

The device package of claim 1, wherein the RDL is a fan-out structure with respect to the semiconductor die unit.

### Claim 4 (depends on 1)

The device package of claim 1, wherein the misalignment of the outline of the semiconductor die unit and device package outline is measured with respect to a reference position of at least one feature on the semiconductor die unit and includes an x-y position or an orientation.

### Claim 5

A device package comprising:
a semiconductor die unit comprising an outline misaligned with a device package outline;
an encapsulant overmolding the semiconductor die unit; and
a build-up structure disposed over both the semiconductor die unit and the encapsulant, the build-up structure comprising:
a redistribution layer (RDL) comprising a first portion aligned with the semiconductor die unit and a second portion aligned with the device package outline, wherein the first portion of the RDL is vertically offset from the semiconductor die unit,
an electrical connecting feature aligned with a bond pad of the semiconductor die unit and disposed between the bond pad and the first portion of the RDL, and
an underbump metallization (UBM) pad disposed over the RDL and aligned with the device package outline.

### Claim 6 (depends on 5)

The device package of claim 5, further comprising an input/output (I/O) interconnect disposed over the build-up structure, wherein the I/O interconnect is aligned with the device package outline.

### Claim 7 (depends on 5)

The device package of claim 5, wherein the second portion of the RDL comprises a UBM via capture pad.

### Claim 8 (depends on 5)

The device package of claim 5, wherein at least a portion of the UBM via capture pad and the UBM pad are connected through a via.

### Claim 9 (depends on 5)

The device package of claim 5, wherein the misalignment of the semiconductor die unit outline and the device package outline is measured with respect to a reference position of at least one feature on the semiconductor die unit and includes an x-y position or orientation different from the device package outline.

### Claim 10 (depends on 5)

The device package of claim 5, wherein the RDL is a fan-out structure with respect to the semiconductor die unit.

### Claim 11

A device package comprising:
a semiconductor die unit misaligned with the device package;
an encapsulant overmolding the semiconductor die unit; and
a build-up structure disposed over the semiconductor die unit, the build-up structure comprising a redistribution layer (RDL) comprising a first portion aligned with a bond pad of the semiconductor die unit and a second portion aligned with the device package, wherein the first portion of the RDL is disposed over and is vertically offset from the bond pad of the semiconductor die unit by an electrical connecting feature.

### Claim 12 (depends on 11)

The device package of claim 11, wherein the RDL comprises a first capture pad, a second capture pad, and a trace.

### Claim 13 (depends on 11)

The device package of claim 11, wherein the RDL is a fan-out structure with respect to the semiconductor die unit.

### Claim 14 (depends on 11)

The device package of claim 11, further comprising:
the encapsulant overmolding at least five sides of the device package; and
the RDL disposed over the semiconductor die unit and the encapsulant overmolding.

### Claim 15 (depends on 11)

The device package of claim 11, further comprising an input/output (I/O) interconnect disposed over the build-up structure, wherein the I/O interconnect is aligned with the device package.