# US 9,520,329 B2 · Fully-depleted silicon-on-insulator transistors

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- Number: US 9,520,329 B2
- Document ID: US9520329B2
- Status: Granted
- Kind: B2
- Application number: 14/882,871
- Filed: 2015-10-14
- Published: 2016-03-17
- Granted: 2016-12-13
- Earliest claimed: 2014-09-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Terence B. Hook; Horacio Mendez
- Web page: https://patentgrep.com/patent/US9520329B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/60: Impurity distributions or concentrations
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 84/857: {comprising an N-type well but not a P-type well}
- H10D 86/01: Manufacture or treatment
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/212: {Through-implantation}
- H10P 95/80: Electrical treatments, e.g. for electroforming
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.

## Claims

### Claim 1

A method of manufacturing a semiconductor structure, comprising:
forming a well in a substrate;
forming a first PFET, a second PFET, and a third PFET on a buried oxide (BOX) layer and over the well;
forming a first NFET, a second NFET, and a third NFET on the BOX layer and over the substrate;
forming a p-type back gate under the second PFET;
forming an n-type back gate under the second NFET;
biasing the well to a first voltage; and
biasing the substrate to a second voltage different than the first voltage,
wherein the first PFET, the second PFET, and the third PFET each has a different threshold voltage, and
the first NFET, the second NFET, and the third NFET each has a different threshold voltage.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the well in the substrate comprises forming an n-well in a p-type substrate.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
tailoring the different threshold voltages of the first PFET, the second PFET, and the third PFET by selectively adjusting: a first dopant concentration of transistor bodies of the first PFET and the second PFET, and a second dopant concentration of a transistor body of the third PFET; and
tailoring the different threshold voltages of the first NFET, the second NFET, and the third NFET by selectively adjusting: a third dopant concentration of transistor bodies of the first NFET and the second NFET, and a fourth dopant concentration of a transistor body of the third NFET.

### Claim 4 (depends on 1)

The method of claim 1, further comprising tailoring the different threshold voltages of the first PFET, the second PFET, and the third PFET by selectively adjusting a thickness of the BOX layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein:
the first PFET is a high threshold voltage PFET;
the second PFET is a regular threshold voltage PFET;
the third PFET is a low threshold voltage PFET;
the first NFET is a high threshold voltage NFET;
the second NFET is a regular threshold voltage NFET; and
the third NFET is a low threshold voltage NFET.

### Claim 6 (depends on 5)

The method of claim 5, wherein:
a threshold voltage of the first PFET is a predetermined amount higher than a threshold voltage of the second PFET;
the threshold voltage of the second PFET is the predetermined amount higher than a threshold voltage of the third PFET;
a threshold voltage of the first NFET is the predetermined amount higher than a threshold voltage of the second NFET; and
the threshold voltage of the second NFET is the predetermined amount higher than a threshold voltage of the third NFET.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
a transistor body of the first PFET and a transistor body of the second PFET each has a first dopant concentration;
a transistor body of the third PFET has a second dopant concentration that is less than the first dopant concentration;
a transistor body of the first NFET and a transistor body of the second NFET each has a third dopant concentration; and
a transistor body of the third NFET has a fourth dopant concentration that is less than the third dopant concentration.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
the second PFET is over a p-type back gate; and
the second NFET is over an n-type back gate.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
the p-type back gate causes a threshold voltage of the second PFET to be less than a threshold voltage of the first PFET; and
the n-type back gate causes a threshold voltage of the second NFET to be less than a threshold voltage of the first NFET.

### Claim 10 (depends on 8)

The method of claim 8, wherein:
the second dopant concentration being less than the first dopant concentration causes a threshold voltage of the third PFET to be less than a threshold voltage of the second PFET; and
the fourth dopant concentration being less than the third dopant concentration causes a threshold voltage of the third NFET to be less than a threshold voltage of the second NFET.

### Claim 11

A method of manufacturing a semiconductor structure, comprising:
forming a well in a substrate;
forming a first PFET, a second PFET, and a third PFET on a buried oxide (BOX) layer and over the well;
forming a first NFET, a second NFET, and a third NFET on the BOX layer and over the substrate;
biasing the well to a first voltage; and
biasing the substrate to a second voltage different than the first voltage,
wherein the first PFET, the second PFET, and the third PFET each has a different threshold voltage,
the first NFET, the second NFET, and the third NFET each has a different threshold voltage;
the first voltage is a power supply voltage (VDD); and
the second voltage is ground.

### Claim 12 (depends on 1)

The method of claim 1, wherein:
the substrate is a p-type substrate that is biased to ground; and
the well is a single n-well in the p-type substrate and extends continuously underneath all of the first PFET, the second PFET, and the third PFET.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the first PFET and the first NFET share a first common gate electrode;
the second PFET and the second NFET share a second common gate electrode; and
the third PFET and the third NFET share a third common gate electrode.

### Claim 14 (depends on 12)

The method of claim 12, wherein:
the p-type substrate directly contacts the BOX layer at a location directly underneath the first NFET; and
the p-type substrate directly contacts the BOX layer at a location directly underneath the third NFET.

### Claim 15 (depends on 12)

The method of claim 12, wherein:
the single n-well directly contacts the BOX layer at a location directly underneath the first PFET;
the single n-well directly contacts the BOX layer at a location directly underneath the third PFET;
the p-type substrate directly contacts the BOX layer at a location directly underneath the first NFET;
the p-type substrate directly contacts the BOX layer at a location directly underneath the third NFET;
the second PFET is over the p-type back gate formed in the single n-well; and
the second NFET is over the n-type back gate formed in the p-type substrate.

### Claim 16 (depends on 12)

The method of claim 12, wherein the single n-well is biased to a power supply voltage using a single n-well contact opening.

### Claim 17 (depends on 11)

The method of claim 11, wherein:
the substrate is a p-type substrate; and
the well is a single n-well in the p-type substrate and extends continuously underneath all of the first PFET, the second PFET, and the third PFET.

### Claim 18 (depends on 17)

The method of claim 17, wherein the single n-well is biased to the power supply voltage using a single n-well contact opening.