# US 9,520,326 B2 · Semiconductor device with high breakdown voltage and manufacture thereof

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- Number: US 9,520,326 B2
- Document ID: US9520326B2
- Status: Granted
- Kind: B2
- Application number: 14/614,795
- Filed: 2015-02-05
- Published: 2015-05-28
- Granted: 2016-12-13
- Earliest claimed: 2011-12-28
- Assignees: Socionext Inc.
- Applicants: Fujitsu Semiconductor Limited
- Inventors: Kazuhiko Takada
- Web page: https://patentgrep.com/patent/US9520326B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 8/022: {of Zener diodes}
- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/156: {Drain regions of DMOS transistors}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/158: {the built-in components being breakdown diodes, e.g. Zener diodes}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10D 8/25: Zener diodes
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
forming a first n-type well by ion implantation of an n-type impurity into a p-type semiconductor substrate;
forming a first isolation film and a second first isolation film in the p-type semiconductor substrate;
forming a second n-type well by ion-implantation of an n-type impurity in the p-type semiconductor substrate, the second n-type well being shallower than the first n-type well;
forming a first p-type backgate region in the first n-type well and a second p-type backgate region in the second n-type well by ion-implantation of a p-type impurity;
forming a first gate electrode that extends from above the first p-type backgate region onto the first isolation film, and forming a second gate electrode that extends from above the second p-type backgate region onto the second isolation film;
forming a first n-type source region in the first p-type backgate region and a second n-type source region in the second p-type backgate region by ion-implantation of an n-type impurity; and
forming a first n-type drain region in the first n-type well at position that is on opposite side to the first n-type source region with respect to the first p-type backgate region and the first isolation film, and forming a second n-type drain region in the second n-type well at position that is on opposite side to the second n-type source region with respect to the second p-type backgate region and the second isolation film by ion-implantation of an n-type impurity.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor device as defined in claim 1, wherein the first isolation film and the second isolation film are formed by forming a first trench and a second trench in the p-type semiconductor substrate, and depositing a first insulation film in the first trench and a second insulation film in the second trench.

### Claim 3 (depends on 1)

The method of manufacturing a semiconductor device as defined in claim 1, wherein the ion implantation for forming the first p-type backgate region and the ion implantation for forming the second p-type backgate region are performed by ion implantations of different conditions.

### Claim 4 (depends on 1)

The method of manufacturing a semiconductor device as defined in claim 1, wherein:
in forming the first n-type well, a third n-type well is formed in the p-type semiconductor substrate;
in forming the first p-type backgate region, a first p-type anode region is formed in the third n-type well; and
in forming the first n-type source region and the second n-type source region, a first n-type cathode region is formed in the first p-type anode region, thereby forming a first Zener diode.

### Claim 5 (depends on 1)

The method of manufacturing a semiconductor device as defined in claim 1, wherein:
in forming of the second n-type well, a fourth n-type well is formed in the p-type semiconductor substrate;
in forming of the second p-type backgate region, a second p-type anode region is formed in the fourth n-type well; and
in forming of the first n-type source region and the second n-type source region, a second n-type cathode region is formed in the second p-type anode region, thereby forming a second Zener diode.