# US 9,520,323 B2 · Microelectronic packages having trench vias and methods for the manufacture thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,323 B2 - Document ID: US9520323B2 - Status: Granted - Kind: B2 - Application number: 13/610,488 - Filed: 2012-09-11 - Published: 2014-03-13 - Granted: 2016-12-13 - Earliest claimed: 2012-09-11 - Assignees: Freescale Semiconductor, Inc. - Applicants: Michael B Vincent; Zhiwei Gong; Scott M Hayes; Douglas G Mitchell - Inventors: Michael B Vincent; Zhiwei Gong; Scott M Hayes; Douglas G Mitchell - Web page: https://patentgrep.com/patent/US9520323B2 ## CPC - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 20/43: Layouts of interconnections - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 72/0198: {batch processes} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/654: Top-view layouts - H10W 72/9413: {on encapsulations} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads. ## Claims ### Claim 1 A method for fabricating a microelectronic package, comprising: depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, the dielectric layer covering the plurality of contact pads; forming a trench via in the dielectric layer exposing the plurality of contact pads therethrough, the trench via formed to include opposing crenulated sidewalls having a plurality of recesses interspersed with a plurality of elongated fingers; sputter etching the plurality of contact pads exposed through the trench via; and forming a plurality of interconnect lines over the dielectric layer each electrically coupled to a different one of the plurality of contact pads; wherein the plurality of elongated fingers have inner terminal ends terminating adjacent the plurality of contact pads, and wherein the inner terminal ends of the plurality of elongated fingers at least partially shield regions of the opposing crenulated sidewalls from deposition of particles dislodged from the plurality of contact pads during sputter etching. ### Claim 2 (depends on 1) A method according to claim 1 wherein the step of depositing comprises depositing the dielectric layer over a second microelectronic device in addition to the first microelectronic device, the second microelectronic device having a plurality of contact pads formed from a different material than are the contact pads included within the first microelectronic device. ### Claim 3 (depends on 2) A method according to claim 2 wherein the contact pads included within the first microelectronic device comprise one of the group consisting of palladium, gold, copper, tin, silver, and lead. ### Claim 4 (depends on 2) A method according to claim 2 further comprising combing the first and second microelectronic devices as a system-in-package. ### Claim 5 (depends on 1) A method according to claim 1 wherein the microelectronic device is included within a fan-out wafer level package. ### Claim 6 (depends on 1) A method according to claim 1 wherein the first microelectronic device is encapsulated within a package body having a device surface through which the first microelectronic device is exposed, and wherein the method further comprises: forming redistribution layers over the device surface and in ohmic contact with the plurality of contact pads, the redistribution layers including the dielectric layer and the plurality of interconnect lines; and producing a contact array electrically coupled to the plurality of contact pads through the redistribution layers. ### Claim 7 (depends on 1) A method according to claim 1 wherein at least one of the plurality of contact pads comprises one of the group consisting of palladium and gold. ### Claim 8 (depends on 1) A method according to claim 1 wherein the opposing crenulated sidewalls comprise recesses located laterally between neighboring ones of the plurality of interconnect lines. ### Claim 9 (depends on 1) A method according to claim 1 wherein forming comprises removing selected portions of the dielectric layer to form a trench exposing the contact pads, while leaving intact portions of the dielectric layer over which the plurality of interconnect lines are formed. ### Claim 10 (depends on 9) A method according to claim 9 wherein the portions of the dielectric layer left intact extend inwardly from the main body of the dielectric layer and terminate adjacent the contact pads. ### Claim 11 (depends on 1) A method according to claim 1 wherein the recesses are each imparted with one of the group consisting of a substantially rectangular planform geometry, a substantially ellipsoidal planform geometry, and a substantially dovetail-shaped planform geometry. ### Claim 12 A method for fabricating a microelectronic package, comprising: depositing a dielectric layer over a first microelectronic device including a row of contact pads, the dielectric layer covering the row of contact pads; forming a trench via in the dielectric layer exposing the plurality of contact pads therethrough, the trench via formed to include opposing crenulated sidewalls having a plurality of recesses adjacent to alternating contact pads in the row of contact pads; sputter etching the plurality of contact pads exposed through the trench via; and forming a plurality of interconnect lines over the dielectric layer each electrically coupled to the plurality of contact pads, the plurality of interconnect lines formed such that a different one of the plurality of interconnect lines extends across each of the plurality of recesses included in at least one of the opposing crenulated sidewalls. ### Claim 13 (depends on 1) A method according to claim 1 further comprising forming the recesses to have repeating planform shapes providing a discontinuous sidewall deposition surface during sputter etching between adjacent contact pads in the plurality of contact pads. ### Claim 14 A method for fabricating a microelectronic package, comprising: depositing a dielectric layer over a microelectronic device having a plurality of contact pads, the dielectric layer covering the plurality of contact pads; forming a crenulated trench via in the dielectric layer exposing the plurality of contact pads therethrough, the crenulated trench via comprising alternating narrow and wide sections, the narrow sections comprising elongated fingers substantially aligned with the plurality of contact pads and having inner terminal ends terminating adjacent the plurality of contact pads; sputter etching the plurality of contact pads exposed through the crenulated trench via; and producing interconnect lines over the dielectric layer and extending into the crenulated trench via to electrically contact the plurality of contact pads. ### Claim 15 (depends on 14) A method according to claim 14 further comprising forming the crenulated trench via such that the wide sections are interspersed with the plurality of contact pads. ### Claim 16 (depends on 14) A method according to claim 14 wherein producing comprises producing the interconnect lines to extend along the plurality of fingers, into the crenulated trench, and to the plurality of contacts. ### Claim 17 (depends on 14) A method according to claim 14 further comprising forming the alternating narrow and wide sections to define recesses in opposing sidewalls of the crenulated trench via, the recesses each comprising a shadow zone at least partially shielded from particles dislodged from the plurality of contact pads during sputter etching. ### Claim 18 (depends on 14) A method according to claim 14 further comprising forming the crenulated trench via such that the alternating narrow and wide sections provide a discontinuous sidewall deposition surface during sputter etching between adjacent contact pads in the plurality of contact pads.