# US 9,520,322 B2 · Semiconductor device and method for manufacturing same

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- Number: US 9,520,322 B2
- Document ID: US9520322B2
- Status: Granted
- Kind: B2
- Application number: 14/321,963
- Filed: 2014-07-02
- Published: 2014-10-23
- Granted: 2016-12-13
- Earliest claimed: 2012-01-06
- Assignees: Toppan Printing Co., Ltd.
- Applicants: Toppan Printing Co., Ltd.
- Inventors: Kenta Hayashi; Katsumi Yamamoto; Makoto Nakamura; Naoyuki Akiyama; Kyosuke Taguchi
- Web page: https://patentgrep.com/patent/US9520322B2

## CPC

- H10W 20/081: {by forming openings in the dielectric parts}
- H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12}
- H10F 39/804: {Containers or encapsulations}
- H10F 39/811: {Interconnections}
- H10P 50/242: {of Group IV materials}
- H10P 50/244: {comprising alternated and repeated etching and passivation steps}
- H10P 50/283: {by chemical means}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate including a first surface in which an integrated circuit and an I/O pad electrically connected to the integrated circuit are formed, and a second surface which is an opposite side to the first surface, where a two-stage through-hole is formed in the semiconductor substrate, the semiconductor substrate including a first shape portion having a tapered shape which has a wall surface and of which a diameter of an opening becomes smaller toward a bottom of the hole from the second surface side to a predetermined position of the semiconductor substrate in a thickness direction, and including a second shape portion having a cylindrical shape which extends from the first shape portion to the I/O pad on the first surface side, and that includes an inorganic insulating film which is formed on the wall surface of the two-stage through-hole and the second surface.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate comprising a first surface and a second surface which is an opposite side to the first surface;
an integrated circuit formed on the first surface of the semiconductor substrate and having a solid-state imaging element;
an I/O pad formed on the first surface and electrically connected to the integrated circuit;
a two-stage through-hole formed in the semiconductor substrate, the two-stage through-hole comprising a first shape portion having a tapered shape which has an inner wall surface and of which a diameter of an opening becomes smaller toward a bottom of the hole from the second surface to a predetermined position of the semiconductor substrate in a thickness direction, and comprising a second shape portion having a cylindrical shape which extends from the first shape portion to the I/O pad on the first surface;
a color filter layer formed on the first surface of the semiconductor substrate and comprising, in a region in which pixels of the solid-state imaging element are formed, an RGB color filter corresponding to each of the pixels and a passivation layer;
a micro-lens array formed on the color filter layer at a location corresponding to the solid-state imaging element;
a cavity dam formed on the I/O pad and surrounding a lateral side of the micro-lens array and the color filter layer;
a glass substrate formed on the cavity dam;
an inorganic insulating film formed on the inner wall surface of the two-stage through-hole and the second surface;
a through-electrode of a metal layer formed on an exposed part of the I/O pad and is formed on the inner wall surface of the two-stage through-hole; and
a wiring pattern formed on the second surface and connected to the through-electrode.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a depth of the second shape portion is equal to or less than four times a diameter of the second shape portion.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the first shape portion comprises a tapered wall surface, and in a cross-section of the first shape portion, the tapered wall surface has a tilt with respect to the second surface which is equal to or greater than 60 degrees and equal to or less than 80 degrees.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a solder resist protecting the second surface and filled into the first shape portion.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the I/O pad which is exposed is formed by an overall etching process without using a resist mask.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a maximum depth of the through-electrode reaches a upper surface of the I/O pad.

### Claim 7

A method for manufacturing a semiconductor device, comprising:
forming, on a first surface of a semiconductor substrate,
an integrated circuit,
an I/O pad electrically connected to the integrated circuit,
a color filter layer comprising, in a region in which pixels of a solid-state imaging element of the integrated circuit are formed,
an RGB color filter corresponding to each of the pixels and a passivation layer, and
a micro-lens array formed at a place corresponding to the solid-state imaging element on the color filter layer;
forming a pattern of a resist for dry-etching having an opening on a second surface which is an opposite side to the first surface;
forming a cavity dam on the I/O pad so as to surround a lateral side of the micro-lens array and the color filter layer;
forming a glass substrate on the cavity dam;
forming a first shape portion opened from the second surface to a predetermined position of the semiconductor substrate in a thickness direction so that a diameter of an opening of the first shape portion in the second surface is larger than a diameter of an opening of the resist for dry-etching and the first shape portion is formed in a tapered shape of which a hole diameter of the first shape portion becomes smaller toward a bottom of the first shape portion, by dry-etching the semiconductor substrate in an RIE mode using a dry-etching apparatus using the resist for dry-etching as a mask;
forming a second shape portion comprising a cylindrical wall surface with the same diameter as that of the opening of the resist for dry-etching which extends from the bottom of the first shape portion to the I/O pad, by performing dry-etching in a Bosch mode using the dry-etching apparatus using the resist for dry-etching as a mask;
forming an inorganic insulating film using a chemical vapor deposition method, on an inner wall surface of a two-stage through-hole constituted by the first shape portion and the second shape portion and on the second surface;
dry-etching an entire surface of the insulating film, and removing the insulating film located on the I/O pad and exposing a part of the I/O pad while leaving the insulating film on the inner wall surface of the two-stage through-hole and on the second surface;
forming a through-electrode by forming a metal film on the exposed part of the I/O pad and on the inner wall surface of the two-stage through-hole; and
forming a wiring pattern on the second surface which is connected to the through-electrode.

### Claim 8 (depends on 7)

The method for manufacturing a semiconductor device according to claim 7, further comprising:
forming a solder resist for protecting the second surface, and
filling the solder resist in the first shape portion.

### Claim 9 (depends on 7)

The method for manufacturing a semiconductor device according to claim 7, wherein the I/O pad is exposed by an overall etching process without using a resist mask.