# US 9,520,321 B2 · Integrated circuits and methods for fabricating integrated circuits with self-aligned vias

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- Number: US 9,520,321 B2
- Document ID: US9520321B2
- Status: Granted
- Kind: B2
- Application number: 14/633,914
- Filed: 2015-02-27
- Published: 2016-09-01
- Granted: 2016-12-13
- Earliest claimed: 2015-02-27
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES, Inc.
- Inventors: Errol Todd Ryan; Sean X. Lin
- Web page: https://patentgrep.com/patent/US9520321B2

## CPC

- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/088: {involving partial etching of via holes}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

## Claims

### Claim 1

A method for fabricating an integrated circuit, the method comprising:
forming a first conductive interconnect line overlying a semiconductor substrate;
after forming the first conductive interconnect line, forming an insulator cap defining a gap overlying the first conductive interconnect line;
depositing an upper interlayer dielectric material over the insulator cap and in the gap over the first conductive interconnect line;
etching a via through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line; and
depositing a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

### Claim 2 (depends on 1)

The method of claim 1 wherein depositing the conductive material into the via to form the conductive via further comprises depositing the conductive material over the upper interlayer dielectric material to form a second conductive interconnect line overlying the upper interlayer dielectric material.

### Claim 3 (depends on 1)

The method of claim 1 wherein etching the via through the upper interlayer dielectric material comprises:
patterning a mask over the upper interlayer dielectric material to define a upper conductive interconnect line region; and
etching the via into the upper interlayer dielectric material through the mask to form the via with an upper end aligned with the mask and a lower end aligned with the gap.

### Claim 4 (depends on 1)

The method of claim 1 wherein etching the via through the upper interlayer dielectric material comprises performing an etch process selective to etching the upper interlayer dielectric faster than etching the insulator cap.

### Claim 5 (depends on 1)

The method of claim 1 further comprising depositing a lower interlayer dielectric material over the semiconductor substrate, wherein forming the insulator cap comprises:
depositing a metal over the lower interlayer dielectric material and the first conductive interconnect line;
annealing the semiconductor substrate to oxidize the metal to form a metal oxide over the lower interlayer dielectric material; and
removing unoxidized metal overlying the first conductive interconnect line.

### Claim 6 (depends on 1)

The method of claim 1 wherein:
forming the first conductive interconnect line comprises forming the first conductive interconnect line in a lower interlayer dielectric material overlying the semiconductor substrate, wherein the first conductive interconnect line has an upper surface at a first height over the semiconductor substrate; and
forming the insulator cap comprises forming the insulator cap over the lower interlayer dielectric material, wherein the insulator cap has a top surface at a second height over the semiconductor substrate greater than the first height.

### Claim 7 (depends on 1)

The method of claim 1 further comprising depositing a lower interlayer dielectric material over the semiconductor substrate, wherein forming the insulator cap comprises:
selectively depositing a temporary cap over the first conductive interconnect line;
depositing an insulator cap material over the lower interlayer dielectric material and the temporary cap;
removing the insulator cap material overlying the temporary cap; and
selectively removing the temporary cap.

### Claim 8 (depends on 7)

The method of claim 7 wherein selectively depositing the temporary cap over the first conductive interconnect line comprises selectively depositing a temporary metal cap over the first conductive interconnect line.

### Claim 9

A method for fabricating an integrated circuit, the method comprising:
forming a first interconnect line overlying a semiconductor substrate;
forming an insulator cap defining a gap overlying the first interconnect line;
depositing a dielectric over the insulator cap and the first interconnect line;
forming a first mask over the dielectric and having an opening exposing a first region of the dielectric;
forming a second mask over the first mask and the dielectric and exposing a second region of the dielectric within the first region and directly overlying the gap;
etching the second region to form a recess in the first region;
removing the second mask;
etching the first region to convert the recess to a via extending into the gap to expose the first interconnect line and to form a trench located above the via; and
depositing a conductive material into the trench and the via to form a second interconnect line and a conductive via in contact with the first interconnect line.

### Claim 10 (depends on 9)

The method of claim 9 wherein:
forming the first interconnect line overlying the semiconductor substrate comprises forming the first interconnect line in a lower interlayer dielectric material overlying the semiconductor substrate, wherein the first interconnect line has an upper surface at a first height over the semiconductor substrate; and
forming the insulator cap comprises forming the insulator cap over the lower interlayer dielectric material, wherein the insulator cap has a top surface at a second height over the semiconductor substrate, and wherein the second height is greater than the first height.

### Claim 11 (depends on 9)

The method of claim 9 wherein:
forming the first interconnect line comprises forming the first interconnect line extending in a first direction;
forming the first mask comprises forming the opening extending in a second direction transverse to the first direction;
etching the first region comprises forming the trench extending in the second direction; and
depositing the conductive material into the trench comprises forming the second interconnect line extending in the second direction.

### Claim 12 (depends on 9)

The method of claim 9 wherein etching the first region to convert the recess to the via extending into the gap to expose the first interconnect line and to form the trench located above the via comprises performing an etch process selective to etching the dielectric faster than etching the insulator cap.

### Claim 13

A method for fabricating an integrated circuit, the method comprising:
forming an insulator cap over a semiconductor substrate and defining a gap;
depositing a barrier layer over the semiconductor and in the gap;
depositing a first conductive material over the barrier layer and in the gap;
recessing the first conductive material;
removing an exposed portion of the barrier liner;
depositing a second conductive material over the first conductive material to form a conductive interconnect line;
depositing an upper interlayer dielectric material over the insulator cap and over the conductive interconnect line;
etching a via through the upper interlayer dielectric material to expose the conductive interconnect line; and
depositing a third conductive material into the via to form a conductive via in contact with the conductive interconnect line.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
forming a block material over the first conductive material before removing the exposed portion of the barrier liner; and
removing the block material after removing the exposed portion of the barrier liner.

### Claim 15 (depends on 13)

The method of claim 13 wherein depositing the third conductive material into the via to form the conductive via further comprises depositing the third conductive material over the upper interlayer dielectric material to form a second conductive interconnect line overlying the upper interlayer dielectric material.

### Claim 16 (depends on 13)

The method of claim 13 wherein:
forming the first conductive interconnect line comprises forming the first conductive interconnect line in a lower interlayer dielectric material overlying the semiconductor substrate, wherein the first conductive interconnect line has an upper surface at a first height over the semiconductor substrate; and
forming the insulator cap comprises forming the insulator cap over the lower interlayer dielectric material, wherein the insulator cap has a top surface at a second height over the semiconductor substrate greater than the first height.