# US 9,520,318 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,318 B2 - Document ID: US9520318B2 - Status: Granted - Kind: B2 - Application number: 14/995,996 - Filed: 2016-01-14 - Published: 2016-05-12 - Granted: 2016-12-13 - Earliest claimed: 2014-01-10 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Satoshi Eguchi; Yoshito Nakazawa - Web page: https://patentgrep.com/patent/US9520318B2 ## CPC - H10W 10/30: Isolation regions comprising PN junctions - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 12/031: {of IGBTs} - H10D 12/441: {Vertical IGBTs} - H10D 30/665: {having edge termination structures} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge - H10D 62/8325: {Silicon carbide} - H10P 30/204: {into Group IV semiconductors} - H10P 30/2044: {into semiconducting carbon, e.g. diamond or semiconducting diamond-like carbon} - H10P 30/208: {of electrically inactive species} - H10P 30/21: {of electrically active species} - H10P 30/22: using masks - H10W 10/031: {of isolation regions comprising PN junctions} - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer. ## Claims ### Claim 1 A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising: (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is an opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, (d) after the step (c), forming a second epitaxial layer of the first conductivity type over the first epitaxial layer extending from the cell region to the peripheral region, (e) after the step (d), forming a plurality of second column regions of the second conductivity type to be electrically coupled with the first column regions, respectively, in such a manner as to be separated from one another in the second epitaxial layer, (f) after the step (e), repeatedly carrying out the same step as the step (d), and the same step as the step (e), and thereby forming a third epitaxial layer including a plurality of third column regions formed therein to an Nth epitaxial layer including a plurality of Nth column regions formed therein in lamination over the second epitaxial layer, and (g) after the step (f), forming an element part at the surface of the Nth epitaxial layer. ### Claim 2 (depends on 1) A method for manufacturing a semiconductor device according to claim 1, wherein, in the cell region, the lower band gap region is formed in a deeper region than half a thickness of a lamination region extending from each of the first column regions to each of the Nth column regions. ### Claim 3 (depends on 1) A method for manufacturing a semiconductor device according to claim 1, wherein the first epitaxial layer is formed of silicon, and wherein the lower band gap impurity is carbon or germanium. ### Claim 4 (depends on 3) A method for manufacturing a semiconductor device according to claim 3, wherein in the step (b), the carbon is doped with a concentration of 0.5 mol % or more and 1.0 mol % or less into the first epitaxial layer, thereby to form the lower band gap region. ### Claim 5 (depends on 3) A method for manufacturing a semiconductor device according to claim 3, wherein in the step (b), the germanium is doped with a concentration of 10 mol % or more and 20 mol % or less into the first epitaxial layer, thereby to form the lower band gap region. ### Claim 6 (depends on 1) A method for manufacturing a semiconductor device according to claim 1, wherein the step (b) uses an ion implantation method. ### Claim 7 (depends on 1) A method for manufacturing a semiconductor device according to claim 1, wherein the step (f) includes doping a higher band gap impurity for making the band gap larger than the band gap of the epitaxial layer before doping into the epitaxial layer in the peripheral region, and thereby forming a higher band gap region in one or more epitaxial layers of the third epitaxial layer to the Nth epitaxial layer, and wherein, in the peripheral region, the higher band gap region is formed in a shallower region than half a thickness of the lamination region extending from each of the first column regions to each of the Nth column regions. ### Claim 8 (depends on 7) A method for manufacturing a semiconductor device according to claim 7, wherein the higher band gap impurity is carbon, and wherein, in the step (b), the carbon is doped with a concentration of 20 mol % or more and 30 mol % or less into the first epitaxial layer, thereby to form the higher band gap region. ### Claim 9 A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising: (a) providing a semiconductor substrate including an epitaxial layer of a first conductivity type formed over a main surface thereof, (b) forming a plurality of trenches in the epitaxial layer extending from the cell region to the peripheral region, (c) filling a semiconductor film of a second conductivity type which is an opposite conductivity type to the first conductivity type in each of the trenches, and thereby forming a plurality of second conductivity type column regions of the second conductivity type in such a manner as to be separated from one another, (d) doping a higher band gap impurity for making a larger band gap than a band gap of the epitaxial layer before doping into the epitaxial layer in the peripheral region, and thereby forming a higher band gap region, and (e) after the step (d), forming an element part at the surface of the epitaxial layer, wherein, in the peripheral region, the higher band gap region is formed in a shallower region than half a depth of each of the second conductivity type column regions. ### Claim 10 (depends on 9) A method for manufacturing a semiconductor device according to claim 9, wherein the step (d) uses an ion implantation method. ### Claim 11 (depends on 9) A method for manufacturing a semiconductor device according to claim 9, wherein the epitaxial layer is formed of silicon, wherein the higher band gap impurity is carbon, and wherein in the step (d), the higher band gap impurity is doped with a concentration of 20 mol % or more and 30 mol % or less into the epitaxial layer, thereby to form the higher band gap region.