# US 9,520,306 B2 · Method of fabricating an integrated circuit (IC) package having a plurality of spaced apart pad portion

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- Number: US 9,520,306 B2
- Document ID: US9520306B2
- Status: Granted
- Kind: B2
- Application number: 13/618,509
- Filed: 2012-09-14
- Published: 2016-01-14
- Granted: 2016-12-13
- Earliest claimed: 1998-06-10
- Assignees: UTAC Headquarters Pte. Ltd.
- Applicants: Geraldine Tsui Yee Lin; Walter de Munnik; Kin Pui Kwan; Wing Him Lau; Kwok Cheung Tsang; Chun Ho Fan; Neil McLellan
- Inventors: Geraldine Tsui Yee Lin; Walter de Munnik; Kin Pui Kwan; Wing Him Lau; Kwok Cheung Tsang; Chun Ho Fan; Neil McLellan
- Web page: https://patentgrep.com/patent/US9520306B2

## CPC

- H10W 74/014: {using batch processing}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 70/042: {Etching}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/354: {comprising polymers}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first surface of the leadframe strip, including the semiconductor die and wire bonds, is encapsulated in a molding material such that at least one surface of the leadframe strip is exposed. The integrated circuit package is singulated from a remainder of the leadframe strip.

## Claims

### Claim 1

A process for fabricating an integrated circuit package, comprising:
providing a leadframe strip having an upper surface and a lower surface;
applying an etch-resist mask to the upper and lower surfaces;
patterning the etch-resist mask to expose portions of the upper and lower surfaces;
selectively etching both the upper and lower surfaces of the leadframe strip by completely etching through portions of the leadframe strip to define a die attach pad and a plurality of contact pads, and only partially etching through portions of the leadframe strip to form a plurality of spaced apart pad portions on the lower surface;
mounting a semiconductor die to said die attach pad;
wire bonding said semiconductor die to respective ones of said contact pads;
encapsulating the upper surface of said leadframe strip, said semiconductor die, and wire bonds in a molding material, the lower surface of said leadframe strip being exposed; and
singulating said integrated circuit package from a remainder of said leadframe strip.

### Claim 2 (depends on 1)

The process according to claim 1, wherein said selectively etching comprises selectively etching such that said plurality of pad portions are shaped and oriented to inhibit entrapment of air during encapsulation.

### Claim 3 (depends on 1)

The process according to claim 1, wherein said selectively etching comprises selectively etching said leadframe strip to define a continuous portion on a first side of the die attach pad and said plurality of pad portions extending from the continuous portion to a second side of the die attach pad.

### Claim 4 (depends on 3)

The process according to claim 3, wherein mounting said semiconductor die comprises mounting said semiconductor die to said first side of the die attach pad.

### Claim 5 (depends on 4)

The process according to claim 4, wherein said selectively etching comprises selectively etching to provide said plurality of pad portions wherein each of said pad portions have a generally square cross-section.

### Claim 6 (depends on 4)

The process according to claim 4, wherein said selectively etching comprises selectively etching to provide said plurality of pad portions wherein each of said pad portions have a generally circular cross-section.

### Claim 7 (depends on 5)

The process according to claim 5, wherein said selectively etching comprises selectively etching to provide said pad portions in a diamond pattern such that sides of said pad portions form an oblique angle with sides of said molding material.

### Claim 8 (depends on 1)

The process according to claim 1, wherein the pad portions form an array.

### Claim 9 (depends on 1)

The process according to claim 1, wherein said selectively etching comprises selectively etching to provide said die attach pad such that each of said plurality of pad portions have a generally square cross-section.

### Claim 10 (depends on 1)

The process according to claim 1, wherein said selectively etching comprises selectively etching to provide said die attach pad such that each of said plurality of pad portions have a generally circular cross-section.

### Claim 11 (depends on 9)

The process according to claim 9, wherein said selectively etching comprises selectively etching to provide said pad portions in a diamond pattern in which sides of said pad portions are at an oblique angle with sides of said molding material.

### Claim 12 (depends on 1)

The process according to claim 1, further comprising applying solder paste to the plurality of contact pads and to said at least one side of said die attach pad.