# US 9,520,304 B2 · Semiconductor package and fabrication method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,304 B2 - Document ID: US9520304B2 - Status: Granted - Kind: B2 - Application number: 14/074,148 - Filed: 2013-11-07 - Published: 2015-02-12 - Granted: 2016-12-13 - Earliest claimed: 2013-08-12 - Assignees: Siliconware Precision Industries Co., Ltd. - Applicants: Siliconware Precision Industries Co., Ltd. - Inventors: Hong-Da Chang; Yi-Che Lai; Chi-Hsin Chiu; Shih-Kuang Chiu - Web page: https://patentgrep.com/patent/US9520304B2 ## CPC - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 70/686: {the multiple insulating layers having different compositions, e.g. polymer layer on glass substrate} - H10W 90/00: Package configurations - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/073: {of die-attach connectors} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed. ## Claims ### Claim 1 A semiconductor package, comprising: a circuit portion having opposite first and second sides; a plurality of semiconductor chips disposed on the first side of the circuit portion; a lamination member disposed on the semiconductor chips so as to increase a strength between the semiconductor chips, wherein the lamination member is a dummy die; and an insulating layer formed on the first side of the circuit portion for encapsulating the semiconductor chips. ### Claim 2 (depends on 1) The package of claim 1, wherein the insulating layer further encapsulates the lamination member. ### Claim 3 (depends on 2) The package of claim 2, wherein the lamination member is exposed from a surface of the insulating layer. ### Claim 4 (depends on 1) The package of claim 1, wherein the insulating layer is flush on sides with the lamination member. ### Claim 5 (depends on 1) The package of claim 1, further comprising an adhesive layer formed between the semiconductor chips and the lamination member. ### Claim 6 (depends on 5) The package of claim 5, wherein the adhesive layer is further formed between the insulating layer and the lamination member. ### Claim 7 (depends on 5) The package of claim 5, wherein the adhesive layer is made of a die attach film (DAF) or a thermal interface material (TIM). ### Claim 8 (depends on 1) The package of claim 1, wherein the insulating layer is further formed between the lamination member and the semiconductor chips. ### Claim 9 (depends on 1) The package of claim 1, further comprising a plurality of conductive elements formed on the second side of the circuit portion. ### Claim 10 (depends on 1) The package of claim 1, wherein the insulating layer is further formed between the circuit portion and the semiconductor chips. ### Claim 11 (depends on 1) The package of claim 1, further comprising an underfill formed between the circuit portion and the semiconductor chips. ### Claim 12 A fabrication method of a semiconductor package, comprising the steps of: providing a semiconductor structure comprising a carrier, a circuit portion formed on the carrier and a plurality of semiconductor chips disposed on the circuit portion; disposing a lamination member on the semiconductor chips, wherein the lamination member is a dummy die; forming an insulating layer on the circuit portion for encapsulating the semiconductor chips; and removing the carrier. ### Claim 13 (depends on 12) The method of claim 12, wherein the carrier is a silicon-containing substrate. ### Claim 14 (depends on 12) The method of claim 12, wherein the semiconductor structure further comprises an underfill formed between the circuit portion and the semiconductor chips. ### Claim 15 (depends on 12) The method of claim 12, wherein the insulating layer is further formed between the circuit portion and the semiconductor chips. ### Claim 16 (depends on 12) The method of claim 12, wherein the lamination member is disposed on the semiconductor chips through an adhesive layer. ### Claim 17 (depends on 16) The method of claim 16, wherein the adhesive layer is made of a die attach film (DAF) or a thermal interface material (TIM). ### Claim 18 (depends on 12) The method of claim 12, wherein the insulating layer further encapsulates the lamination member. ### Claim 19 (depends on 18) The method of claim 18, after forming the insulating layer, further comprising exposing the lamination member from a surface of the insulating layer. ### Claim 20 (depends on 12) The method of claim 12, after removing the carrier, further comprising exposing the circuit portion so as to form a plurality of conductive elements on the circuit portion. ### Claim 21 A fabrication method of a semiconductor package, comprising the steps of: providing a semiconductor structure comprising a carrier, a circuit portion formed on the carrier and a plurality of semiconductor chips disposed on the circuit portion; forming an insulating layer on the circuit portion for encapsulating the semiconductor chips; disposing a lamination member on the semiconductor chips and the insulating layer, wherein the lamination member is a dummy die; and removing the carrier. ### Claim 22 (depends on 21) The method of claim 21, wherein the carrier is a silicon-containing substrate. ### Claim 23 (depends on 21) The method of claim 21, wherein the semiconductor structure further comprises an underfill formed between the circuit portion and the semiconductor chips. ### Claim 24 (depends on 21) The method of claim 21, wherein the insulating layer is further formed between the circuit portion and the semiconductor chips. ### Claim 25 (depends on 21) The method of claim 21, before disposing the lamination member, further comprising exposing the semiconductor chips from a surface of the insulating layer. ### Claim 26 (depends on 25) The method of claim 25, wherein the lamination member is disposed on the semiconductor chips and the insulating layer through an adhesive layer. ### Claim 27 (depends on 26) The method of claim 26, wherein the adhesive layer is made of a die attach film (DAF) or a thermal interface material (TIM). ### Claim 28 (depends on 21) The method of claim 21, after removing the carrier, further comprising exposing the circuit portion so as to form a plurality of conductive elements on the circuit portion. ### Claim 29 A fabrication method of a semiconductor package, comprising the steps of: providing a semiconductor structure comprising a carrier, a circuit portion formed on the carrier and a plurality of semiconductor chips disposed on the circuit portion; providing a lamination member having an insulating layer and disposing the lamination member on the circuit portion through the insulating layer, wherein the insulating layer encapsulates the semiconductor chips, wherein the lamination member is a dummy die; and removing the carrier. ### Claim 30 (depends on 29) The method of claim 29, wherein the carrier is a silicon-containing substrate. ### Claim 31 (depends on 29) The method of claim 29, wherein the semiconductor structure further comprises an underfill formed between the circuit portion and the semiconductor chips. ### Claim 32 (depends on 29) The method of claim 29, wherein the insulating layer is further formed between the circuit portion and the semiconductor chips. ### Claim 33 (depends on 29) The method of claim 29, wherein the insulating layer is further formed between the lamination member and the semiconductor chips. ### Claim 34 (depends on 29) The method of claim 29, after removing the carrier, further comprising exposing the circuit portion so as to form a plurality of conductive elements on the circuit portion.