# US 9,520,300 B2 · Semiconductor devices and methods of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,300 B2 - Document ID: US9520300B2 - Status: Granted - Kind: B2 - Application number: 14/606,970 - Filed: 2015-01-27 - Published: 2015-11-19 - Granted: 2016-12-13 - Earliest claimed: 2014-05-15 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Wookyung You; Jongmin Baek; Sanghoon Ahn; Sangho Rha; Naein Lee - Web page: https://patentgrep.com/patent/US9520300B2 ## CPC - H10W 20/46: comprising air gaps - H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)} - H10P 14/6336: {in the presence of a plasma [PECVD]} - H10P 14/6536: {by exposure to radiation, e.g. visible light} - H10P 14/6538: {by exposure to UV light} - H10P 14/665: {Porous materials} - H10P 14/6681: {the precursor containing a compound comprising Si} - H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC} - H10P 50/28: of insulating materials - H10P 50/73: {using masks for insulating materials} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/072: {of dielectric parts comprising air gaps} - H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)} - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns. ## Claims ### Claim 1 A method of fabricating a semiconductor device, the method comprising: forming an interlayer insulating layer on a substrate, the interlayer insulating layer comprising: a first portion being adjacent to the substrate and having a first pore density; a second portion formed on the first portion; and a third portion formed on the second portion and having a second pore density higher than the first pore density, and a pore density of the second portion gradually increasing toward the third portion; forming conductive patterns penetrating the third portion of the interlayer insulating layer; etching the third portion of the interlayer insulating layer to reduce a height of the interlayer insulating layer; and forming a capping insulation layer on the conductive patterns, wherein an air gap is formed between the conductive patterns. ### Claim 2 (depends on 1) The method of claim 1, wherein the pore density of the second portion of the interlayer insulating layer is higher than or equal to the first pore density and is lower than or equal to the second pore density. ### Claim 3 (depends on 1) The method of claim 1, wherein forming the interlayer insulating layer is performed by a deposition process having a first deposition duration and a second deposition duration, the deposition process being performed by using a silicon precursor gas, an organic precursor gas, and a porogen gas, wherein supply rates of the organic precursor gas and the porogen gas are gradually increased in the first deposition duration, and wherein supply rates of the silicon precursor gas, the organic precursor gas, and the porogen gas are constant in the second deposition duration. ### Claim 4 (depends on 1) The method of claim 1, wherein forming the interlayer insulating layer comprises: forming porogen portions in the interlayer insulating layer; and forming pores in the interlayer insulating layer by removing the porogen portions. ### Claim 5 (depends on 4) The method of claim 4, wherein forming the pores comprises applying heat or an ultraviolet ray to the interlayer insulating layer to remove a hydrocarbon material included in the porogen portions. ### Claim 6 (depends on 1) The method of claim 1, wherein an atomic ratio of carbon in the third portion of the interlayer insulating layer is greater than that of the first portion of the interlayer insulating layer, and wherein an atomic ratio of carbon in the second portion of the interlayer insulating layer is gradually increased toward the third portion of the interlayer insulating layer. ### Claim 7 (depends on 1) The method of claim 1, wherein an etch rate of the third portion of the interlayer insulating layer is higher than that of the first portion of the interlayer insulating layer. ### Claim 8 (depends on 1) The method of claim 1, wherein the substrate includes a first region and a second region and the conductive patterns are formed in the first region, and wherein etching the third portion of the interlayer insulating layer comprises: forming a mask pattern exposing the interlayer insulating layer of the first region; and etching the third portion of the interlayer insulating layer of the first region using the mask pattern as an etch mask. ### Claim 9 (depends on 1) The method of claim 1, wherein a bottom surface, which is formed between the conductive patterns after etching the third portion, of the interlayer insulating layer is disposed at the same level as or a higher level than bottom surfaces of the conductive patterns. ### Claim 10 (depends on 1) The method of claim 1, wherein forming the air gap comprises: forming a groove between the conductive patterns by etching the third portion of the interlayer insulating layer, and forming the capping insulation layer to close an upper portion of the groove. ### Claim 11 A method of fabricating a semiconductor device, the method comprising: forming an interlayer insulating layer on a substrate; forming recesses in the interlayer insulating layer; forming conductive patterns filling the recesses; removing an upper portion of the interlayer insulating layer disposed between the conductive patterns to reduce a height of the interlayer insulating layer; and forming a capping insulation layer on the conductive patterns to form an air gap between the conductive patterns, wherein the interlayer insulating layer is formed by a deposition process including a first deposition duration and a second deposition duration, wherein a silicon precursor gas, an organic precursor gas, and a porogen gas are supplied during the deposition process, wherein supply rates of the organic precursor gas and the porogen gas gradually increase in the first deposition duration, and wherein supply rates of the silicon precursor gas, the organic precursor gas, and the porogen gas are constant in the second deposition duration. ### Claim 12 (depends on 11) The method of claim 11, wherein forming the interlayer insulating layer further comprises forming pores in the interlayer insulating layer, wherein the pores are formed by removing porogen portions that are formed by the porogen gas. ### Claim 13 (depends on 12) The method of claim 12, wherein a pore density of the interlayer insulating layer formed during the second deposition duration is higher than that of the interlayer insulating layer formed during the first deposition duration. ### Claim 14 (depends on 12) The method of claim 12, wherein a pore density of the interlayer insulating layer formed during the first deposition duration is gradually increased from a bottom surface toward a top surface of the interlayer insulating layer formed during the first deposition duration. ### Claim 15 (depends on 11) The method of claim 11, wherein forming the interlayer insulating layer further comprises supplying the silicon precursor gas to form a glue layer on the substrate, wherein the glue layer is formed before the organic precursor gas and the porogen gas are supplied. ### Claim 16 (depends on 11) The method of claim 11, wherein an atomic ratio of carbon in the interlayer insulating layer formed during the second deposition duration is greater than that of the interlayer insulating layer formed during the first deposition. ### Claim 17 A method of fabricating a semiconductor device, the method comprising: forming an interlayer insulating layer on a substrate, the interlayer insulating layer comprising a lower portion being adjacent to the substrate, a middle portion on the lower portion, and an upper portion on the middle portion, wherein the upper portion of the interlayer insulating layer has recesses; forming conductive patterns in the recesses; etching the upper portion of the interlayer insulating layer to reduce a height of the interlayer insulating layer; and forming a capping insulation layer on the conductive patterns, wherein an air gap is formed between the conductive patterns, wherein a pore density of the lower portion of the interlayer insulating layer is higher than that of the upper portion of the interlayer insulating layer, wherein a pore density of the middle portion is gradually increased toward the upper portion. ### Claim 18 (depends on 17) The method of claim 17, wherein the pore density of the middle portion of the interlayer insulating layer is higher than or equal to the pore density of the lower portion of the interlayer insulating layer and is lower than or equal to the pore density of the upper portion of the interlayer insulating layer. ### Claim 19 (depends on 17) The method of claim 17, wherein forming the interlayer insulating layer is performed by a deposition process having a first deposition duration and a second deposition duration, the deposition process being performed by using a silicon precursor gas, an organic precursor gas, and a porogen gas, wherein supply rates of the organic precursor gas and the porogen gas are gradually increased during the first deposition duration, and wherein supply rates of the silicon precursor gas, the organic precursor gas, and the porogen gas are constant during the second deposition duration. ### Claim 20 (depends on 17) The method of claim 17, wherein an atomic ratio of carbon in the upper portion of the interlayer insulating layer is greater than that of the lower portion of the interlayer insulating layer, and wherein an atomic ratio of carbon in the middle portion of the interlayer insulating layer is gradually increased toward the upper portion of the interlayer insulating layer.