# US 9,520,292 B2 · Aging-based leakage energy reduction method and system

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- Number: US 9,520,292 B2
- Document ID: US9520292B2
- Status: Granted
- Kind: B2
- Application number: 14/407,072
- Filed: 2013-01-06
- Published: 2015-06-11
- Granted: 2016-12-13
- Earliest claimed: 2013-01-06
- Assignees: Empire Technology Development LLC
- Applicants: Empire Technology Development LLC
- Inventors: Miodrag Potkonjak
- Web page: https://patentgrep.com/patent/US9520292B2

## CPC

- H03K 17/161: {in field-effect transistor switches}
- G06F 30/30: Circuit design
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 95/80: Electrical treatments, e.g. for electroforming
- G06F 2119/04: Ageing analysis or optimisation against ageing
- G06F 2119/06: Power analysis or power optimisation
- G06F 2119/12: Timing analysis or timing optimisation
- H03K 2217/0036: Means reducing energy consumption
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.

## Claims

### Claim 1

A method to reduce leakage energy associated with a post-silicon target circuit, the method comprising:
selecting a plurality of gates in the target circuit to be aged;
determining an extent to which to age the selected plurality of gates;
identifying a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;
based on the targeted metric, aging, to the determined extent, the first set of gates; and
based on the targeted metric, aging, to less than the determined extent, the second set of gates.

### Claim 2 (depends on 1)

The method of claim 1, further comprising characterizing the plurality of gates at a transistor or gate level.

### Claim 3 (depends on 1)

The method of claim 1, wherein determining the extent to which to age the selected plurality of gates comprises assigning a first weight and a second weight to each gate in the target circuit based on a contribution of the each gate to energy consumption and critical timing constraints of the target circuit, wherein the first weight is associated with leakage energy, and the second weight is associated with timing.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
formulating a satisfiability (SAT) problem that includes a first set of objectives for the first set of gates and a second set of objectives for the second set of gates to reduce the leakage energy associated with the target circuit; and
selecting a set of candidate input vectors for the target circuit by iteratively solving the SAT problem by removing one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight,
wherein aging to the determined extent the first set of gates and aging to less than the determined extent the second set of gates comprise applying the set of candidate input vectors to the plurality of gates to stress the plurality of gates.

### Claim 5 (depends on 4)

The method of claim 4, further comprising selecting a subset of input vectors from the set of candidate input vectors in such a way that the timing constraint associated with the target circuit is also satisfied.

### Claim 6 (depends on 5)

The method of claim 5, further comprising setting the timing constraint in a linear program that includes an objective of reducing leakage energy associated with the first set of gates.

### Claim 7 (depends on 6)

The method of claim 6, further comprising approximating a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates in the target circuit.

### Claim 8 (depends on 5)

The method of claim 5, further comprising:
providing the subset of input vectors to the target circuit to age at least some of the first set of gates more than the second set of gates.

### Claim 9 (depends on 1)

The method of claim 1, further comprising applying adaptive body bias (ABB) to the target circuit based on the targeted metric.

### Claim 10 (depends on 1)

The method of claim 1, wherein aging the plurality of gates in the target circuit reduces a hot spot in the target circuit.

### Claim 11 (depends on 1)

The method of claim 1, wherein aging the plurality of gates in the target circuit improves yield.

### Claim 12 (depends on 1)

The method of claim 1, wherein aging to the determined extent the first set of gates and aging to less than the determined extent the second set of gates comprises applying a set of candidate input vectors to the plurality of gates to stress the plurality of gates.

### Claim 13

A non-transitory computer-readable medium that includes instructions to reduce leakage energy associated with a post-silicon target circuit, which in response to execution by a processor, cause the processor to perform or control performance of:
select a plurality of gates in the target circuit to be aged;
determine an extent to which to age the selected plurality of gates;
identify a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;
based on the targeted metric, age, to the determined extent, the first set of gates; and
based on the targeted metric, age, to less than the determined extent, the second set of gates.

### Claim 14 (depends on 13)

The non-transitory computer-readable medium of claim 13, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of characterize the plurality of gates at a transistor or gate level.

### Claim 15 (depends on 13)

The non-transitory computer-readable medium of claim 13, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:
assign a first weight and a second weight to each gate in the target circuit based on a contribution of the each gate to energy consumption and critical timing constraints of the target circuit, wherein the first weight is associated with leakage energy, and the second weight is associated with timing.

### Claim 16 (depends on 15)

The non-transitory computer-readable medium of claim 15, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:
formulate a satisfiability (SAT) problem that includes a first set of objectives for the first set of gates and a second set of objectives for the second set of gates to reduce the leakage energy associated with the target circuit; and
select a set of candidate input vectors for the target circuit through an iterative solution of the SAT problem by removal of one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight,
wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the instructions, in response to execution by the processor, cause the processor to perform or control performance of:
apply the set of candidate input vectors to the plurality of gates to stress the plurality of gates.

### Claim 17 (depends on 16)

The non-transitory computer-readable medium of claim 16, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:
select a subset of input vectors from the set of candidate input vectors in such a way that the timing constraint associated with the target circuit is also satisfied.

### Claim 18 (depends on 17)

The non-transitory computer-readable medium of claim 17, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:
set the timing constraint in a linear program that includes an objective to reduce leakage energy associated with the first set of gates.

### Claim 19 (depends on 18)

The non-transitory computer-readable medium of claim 18, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:
approximate a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates in the target circuit.

### Claim 20 (depends on 17)

The non-transitory computer-readable medium of claim 17, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:
provide the subset of input vectors to the target circuit to age at least some of the first set of gates more than the second set of gates.

### Claim 21 (depends on 13)

The non-transitory computer-readable medium of claim 13, further including instructions, which in response to execution by the processor, cause the processor to perform or control performance of:
apply adaptive body bias (ABB) to the target circuit based on the targeted metric.

### Claim 22 (depends on 13)

The non-transitory computer-readable medium of claim 13, wherein aging of the plurality of gates in the target circuit reduces a hot spot in the target circuit.

### Claim 23 (depends on 13)

The non-transitory computer-readable medium of claim 13, wherein the aging of the plurality of gates in the target circuit improves yield.

### Claim 24 (depends on 13)

The non-transitory computer-readable medium of claim 13, wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the instructions, in response to execution by the processor, cause the processor to perform or control performance of:
apply a set of candidate input vectors to the plurality of gates to stress the plurality of gates.

### Claim 25

A computing device coupled to a post-silicon target circuit and configured to reduce leakage energy associated with the post-silicon target circuit, comprising:
a programmable unit; and
a processor, coupled to the programmable unit, wherein the processor is configured to:
select a plurality of gates in the target circuit to be aged;
determine an extent to which to age the selected plurality of gates;
identify a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;
based on the targeted metric, age, to the determined extent, the first set of gates; and
based on the targeted metric, age, to less than the determined extent, the second set of gates.

### Claim 26 (depends on 25)

The computing device of claim 25, wherein the processor is further configured to characterize the plurality of gates at a transistor or gate level.

### Claim 27 (depends on 25)

The computing device of claim 25, wherein the processor is further configured to:
assign a first weight and a second weight to each gate in the target circuit based on a contribution of the each gate to energy consumption and critical timing constraints of the target circuit, wherein the first weight is associated with leakage energy, and the second weight is associated with timing.

### Claim 28 (depends on 27)

The computing device of claim 27, wherein the processor is further configured to:
formulate a satisfiability (SAT) problem that includes a first set of objectives for the first set of gates and a second set of objectives for the second set of gates to reduce the leakage energy associated with the target circuit; and
select a set of candidate input vectors for the target circuit through an iterative solution of the SAT problem by removal of one or more gates from being considered in the first set of objectives and the second set of objectives based on the first weight and the second weight,
wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the processor is configured to apply the set of candidate input vectors to the plurality of gates to stress the plurality of gates.

### Claim 29 (depends on 28)

The computing device of claim 28, wherein the processor is configured to select a subset of input vectors from the set of candidate input vectors in such a way that the timing constraint associated with the target circuit is also satisfied.

### Claim 30 (depends on 29)

The computing device of claim 29, wherein the processor is further configured to set the timing constraint in a linear program that includes an objective to reduce leakage energy associated with the first set of gates.

### Claim 31 (depends on 30)

The computing device of claim 30, wherein the processor is further configured to approximate a possible critical path in the target circuit based on an initial longest path in terms of delays associated with a subset of gates in the target circuit.

### Claim 32 (depends on 29)

The computing device of claim 29, wherein the processor is further configured to load the subset of input vectors in the programmable unit, so that the subset of input vectors are applied to the target circuit to age at least some of the first set of gates more than the second set of gates.

### Claim 33 (depends on 25)

The computing device of claim 25, wherein the processor is further configured to apply adaptive body bias (ABB) to the target circuit based on the targeted metric.

### Claim 34 (depends on 25)

The computing device of claim 25, wherein to age to the determined extent the first set of gates and to age to less than the determined extent the second set of gates, the processor is configured to apply a set of candidate input vectors to the plurality of gates to stress the plurality of gates.