# US 9,520,291 B2 · Method of providing an implanted region in a semiconductor structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,291 B2 - Document ID: US9520291B2 - Status: Granted - Kind: B2 - Application number: 14/757,671 - Filed: 2015-12-23 - Published: 2016-07-07 - Granted: 2016-12-13 - Earliest claimed: 2014-12-30 - Assignees: Imec Vzw - Applicants: Imec Vzw - Inventors: Zheng Tao; Kaidong Xu - Web page: https://patentgrep.com/patent/US9520291B2 ## CPC - H10P 32/171: {being group IV material} - H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 86/011: {comprising FinFETs} - H10P 30/22: using masks - H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase - H10P 32/1406: {by ion implantation} - H10P 50/00: Etching of wafers, substrates or parts of devices - H10P 50/642: {Chemical etching} - H10P 50/691: {for Group IV materials or Group III-V materials} - H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks} - H10P 50/73: {using masks for insulating materials} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to an aspect of the present inventive concept there is provided a method of providing an implanted region in a semiconductor structure including a first region and a second region, the method comprising: providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon (SOC) layer, and a second sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass (SOG) layer; subjecting the semiconductor structure to an ion implantation process wherein an extension of the first implantation mask is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed wherein the second region is implanted; forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial layer includes carbon; removing the second sacrificial layer at the first region by etching, wherein the third sacrificial layer protects the second region from being affected by said etching; and removing the first sacrificial layer at the first region and the third sacrificial layer at the second region by etching. ## Claims ### Claim 1 A method of providing an implanted region in a semiconductor structure including a first region and a second region, the method comprising: providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon layer, and a second sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass layer; subjecting the semiconductor structure to an ion implantation process, wherein an extension of the first implantation mask is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed where the second region is implanted; forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial layer includes carbon; removing the second sacrificial layer at the first region by etching, wherein the third sacrificial layer protects the second region from being affected by the etching, and removing the first sacrificial layer at the first region and the third sacrificial layer at the second region by etching. ### Claim 2 (depends on 1) The method according to claim 1, wherein the first sacrificial layer and the third sacrificial layer are arranged to be etched by a same etchant. ### Claim 3 (depends on 1) The method according to claim 1, wherein the third sacrificial layer is formed to cover the second region and the second sacrificial layer at the first region, and wherein the method further comprises: etching an exposed surface of the third sacrificial layer until the second sacrificial layer at the first region is exposed and, thereafter removing the second sacrificial layer at the first region by etching. ### Claim 4 (depends on 1) The method according to claim 1, further comprising, subsequent to removing the first sacrificial layer at the first region and the third sacrificial layer at the second region: providing a second implantation mask covering the second region of the semiconductor structure, the second implantation mask including a first sacrificial layer, wherein the first sacrificial layer of the second implantation mask is formed as a spin-on-carbon layer, and a second sacrificial layer, wherein the second sacrificial layer of the second implantation mask is formed as a spin-on-glass layer; subjecting the semiconductor structure to an ion implantation process, wherein an extension of the second implantation mask is such that ion implantation in the second region is counteracted and ion implantation in the first region is allowed where the first region is implanted; forming a fourth sacrificial layer covering the first region of the semiconductor structure, wherein the fourth sacrificial layer includes carbon; removing the second sacrificial layer of the second implantation mask at the second region by etching, wherein the fourth sacrificial layer protects the first region from being affected by the etching; and removing the first sacrificial layer of the second implantation mask at the second region and the fourth sacrificial layer at the first region by etching. ### Claim 5 (depends on 4) The method according to claim 4, wherein the first sacrificial layer and the fourth sacrificial layer are arranged to be etched by a same etchant. ### Claim 6 (depends on 4) The method according to claim 4, wherein the fourth sacrificial layer is formed to cover the first region and the second sacrificial layer of the second implantation mask at the second region, and wherein the method further comprises: etching an exposed surface of the fourth sacrificial layer until the second sacrificial layer of the second implantation mask at the second region is exposed; and thereafter removing the second sacrificial layer of the second implantation mask at the second region by etching. ### Claim 7 (depends on 1) The method according to claim 1, further comprising, subsequent to forming the third sacrificial layer at the second region of the semiconductor structure and prior to removing the first sacrificial layer at the first region and the third sacrificial layer at the second region by etching: forming a fourth sacrificial layer at the first and the second region, wherein the fourth sacrificial layer is formed as a spin-on-glass layer; removing the fourth sacrificial layer at the first region by etching wherein the first sacrificial layer protects the first region from being affected by the etching; removing the first sacrificial layer at the first region, wherein the third sacrificial layer at the second region and the fourth sacrificial layer at the second region forms a second implantation mask covering the second region of the semiconductor structure; and subjecting the semiconductor structure to an ion implantation process, wherein an extension of the second implantation mask is such that ion implantation in the second region is counteracted and ion implantation in the first region is allowed where the first region is implanted. ### Claim 8 (depends on 7) The method according to claim 7, wherein the fourth sacrificial layer is formed prior to or subsequent to removing the second sacrificial layer at the first region by etching. ### Claim 9 (depends on 7) A method according to claim 7, further comprising, subsequent to implanting the first region: forming a fifth sacrificial layer at the first region of the semiconductor structure, wherein the fifth sacrificial layer includes carbon; removing the fourth sacrificial layer of the second implantation mask at the second region by etching, wherein the fifth sacrificial layer protects the first region from being affected by the etching; and removing the third sacrificial layer at the second region and the fifth sacrificial layer at the first region by etching. ### Claim 10 (depends on 9) The method according to claim 9, wherein the third sacrificial layer and the fifth sacrificial layer are arranged to be etched by a same etchant. ### Claim 11 (depends on 9) The method according to claim 9, wherein the fifth sacrificial layer is formed to cover the first region and the fourth sacrificial layer at the second region, and wherein the method further comprises etching an exposed surface of the fifth sacrificial layer until the fourth sacrificial layer at the second region is exposed and, thereafter removing the fourth sacrificial layer of the second implantation mask at the second region by etching. ### Claim 12 (depends on 11) The method according to claim 11, wherein the third sacrificial layer is formed as a spin-on-carbon layer. ### Claim 13 (depends on 12) The method according to claim 12, wherein the fourth sacrificial layer is formed as a spin-on-carbon layer. ### Claim 14 (depends on 12) The method according to claim 12, wherein the fifth sacrificial layer is formed as a spin-on-carbon layer. ### Claim 15 (depends on 12) The method according to claim 12, wherein the first region of the semiconductor structure includes at least one fin-shaped feature and the second region of the semiconductor structure includes at least one fin-shaped feature. ### Claim 16 A method of providing an implanted region in a semiconductor structure including a first region and a second region, the method comprising: providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon layer, and a second sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass layer; subjecting the semiconductor structure to an ion implantation process, wherein an extension of the first implantation mask is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed where the second region is implanted; forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial layer includes carbon; and removing the first sacrificial layer of the first implantation mask, the second sacrificial layer of the first implantation mask and the third sacrificial layer by a same etching process including an etchant comprising fluoride. ### Claim 17 (depends on 16) The method according to claim 16, wherein the third sacrificial layer is formed to cover the second region and the second sacrificial layer at the first region, the method further comprising: reducing a thickness of the third sacrificial layer at the first region and at the second region by etching an exposed surface of the third sacrificial layer until a residual portion of the third sacrificial layer remains on the second sacrificial layer, or until the second sacrificial layer at the first region is exposed, and thereafter removing the first sacrificial layer, the second sacrificial layer and the third sacrificial layer, and the residual portion if present on the second sacrificial layer, by the same etching process.