# US 9,520,222 B2 · Wiring board and method for manufacturing wiring board

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- Number: US 9,520,222 B2
- Document ID: US9520222B2
- Status: Granted
- Kind: B2
- Application number: 14/041,638
- Filed: 2013-09-30
- Published: 2014-04-03
- Granted: 2016-12-13
- Earliest claimed: 2012-09-28
- Assignees: Ibiden Co., Ltd.
- Applicants: Ibiden Co., Ltd.
- Inventors: Ryojiro Tominaga; Keinosuke Ino
- Web page: https://patentgrep.com/patent/US9520222B2

## CPC

- H01F 27/2804: {Printed windings}
- H01F 41/005: {Impregnating or encapsulating (insulating of windings H01F41/12)}
- H05K 1/165: {incorporating printed inductors}
- H01F 27/2809: {on stacked layers}
- H01F 2017/002: {Details of via holes for interconnecting the layers}
- H05K 1/0216: {Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215)}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H05K 2201/0191: wherein the thickness of the dielectric plays an important role
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- Y10T 156/10: Methods of surface bonding and/or assembly therefor
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A wiring board includes a substrate including first insulation layers, a second insulation layer on the first layers, a third insulation layer on the second layer, and a plain conductor on the third layer. The substrate has inductor forming portion in which inductor patterns are formed on the first layers and first via conductors formed in the first layers such that the first via conductors connect the inductor patterns through the first layers, the substrate has a land on the second layer and a second via conductor in the second layer such that the second via conductor connects the land and the outermost inductor pattern, the substrate has a third via conductor in the third layer such that the third via conductor connects the plain conductor and land and has the central axis passing through the center of the third via conductor inside projected region of the second via conductor.

## Claims

### Claim 1

A wiring board, comprising:
a substrate comprising a plurality of first insulation layers, a plurality of second insulation layers formed on the outermost first insulation layers of the first insulation layers, respectively, a plurality of third insulation layers formed on the second insulation layers, respectively, and a plurality of plain conductors formed on the third insulation layers, respectively,
wherein the substrate has an inductor forming portion in which a plurality of inductor patterns is formed on the plurality of first insulation layers, respectively, and a plurality of first via conductors formed in the first insulation layers, respectively, such that the first via conductors are connecting the inductor patterns through the first insulation layers, the substrate has a plurality of land structures formed on the second insulation layers, respectively, and a plurality of second via conductors formed in the second insulation layers, respectively, such that the plurality of second via conductors is connecting the land structures and the outermost inductor patterns of the inductor patterns, respectively, the substrate has a plurality of third via conductors formed in the third insulation layers, respectively, such that the plurality of third via conductors is connecting the plain conductors and the land structures, respectively, and each has a central axis passing through the center of each of the third via conductors inside a projected region of a respective one of the second via conductors and that the plurality of outermost inductor patterns of the inductor patterns is formed in the substrate such that the outermost inductor patterns are separated 100 μm or more from the plain conductors, respectively.

### Claim 2 (depends on 1)

The wiring board according to claim 1, wherein each of the land structures has a thickness which is less than a thickness of each of the inductor patterns.

### Claim 3 (depends on 1)

The wiring board according to claim 1, wherein the substrate has no other conductor between the outermost inductor patterns of the inductor patterns and the plain conductors except the second via conductors, the third via conductors and the land portions.

### Claim 4 (depends on 1)

The wiring board according to claim 1, wherein each of the first insulation layers, second insulation layers and third insulation layers has an inorganic fiber reinforcing material.

### Claim 5 (depends on 1)

The wiring board according to claim 1, wherein each of the plain conductors has a plurality of mesh holes.

### Claim 6 (depends on 1)

The wiring board according to claim 1, further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern, wherein the fourth insulation layer does not contain an inorganic fiber reinforcing material.

### Claim 7 (depends on 6)

The wiring board according to claim 6, wherein each of the inductor patterns has a thickness which is greater than a thickness of the conductive pattern.

### Claim 8 (depends on 1)

The wiring board according to claim 1, wherein each of the inductor patterns comprises a metal foil formed on a respective layer of the first insulation layers, an electroless plated film on the metal foil, and an electrolytic plated film on the electroless plated film.

### Claim 9 (depends on 1)

The wiring board according to claim 1, further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern.

### Claim 10 (depends on 9)

The wiring board according to claim 9, wherein the inductor pattern has a thickness which is greater than a thickness of the conductive pattern.

### Claim 11 (depends on 1)

The wiring board according to claim 1, wherein each of the land structures has a thickness which is less than a thickness of each of the inductor patterns, and each of the inductor patterns comprises a metal foil formed on a respective layer of the first insulation layers, an electroless plated film on the metal foil, and an electrolytic plated film on the electroless plated film.

### Claim 12 (depends on 1)

The wiring board according to claim 1, further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern, wherein the fourth insulation layer does not contain an inorganic fiber reinforcing material, and each of the first insulation layers, second insulation layers and third insulation layers has an inorganic fiber reinforcing material.

### Claim 13 (depends on 12)

The wiring board according to claim 12, wherein each of the inductor patterns has a thickness which is greater than a thickness of the conductive pattern.

### Claim 14 (depends on 1)

The wiring board according to claim 1, further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern, wherein the fourth insulation layer does not contain an inorganic fiber reinforcing material, and the respective one of the plain conductors has a plurality of mesh holes.

### Claim 15 (depends on 1)

The wiring board according to claim 1, further comprising:
a buildup layer formed on the substrate and configured to mount a semiconductor electronic component such that the semiconductor electronic component is positioned directly over the inductor forming portion of the substrate.

### Claim 16 (depends on 1)

The wiring board according to claim 1, further comprising:
a buildup layer formed on the substrate and configured to mount a semiconductor electronic component such that the semiconductor electronic component is positioned directly over the inductor forming portion of the substrate,
wherein the buildup layer comprises a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern.