# US 9,520,203 B2 · Semiconductor memory device for performing both of static test and dynamic test during wafer burn-in test and method for operating the same

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- Number: US 9,520,203 B2
- Document ID: US9520203B2
- Status: Granted
- Kind: B2
- Application number: 14/546,720
- Filed: 2014-11-18
- Published: 2015-11-19
- Granted: 2016-12-13
- Earliest claimed: 2014-05-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sung-Yub Lee; Geun-Il Lee
- Web page: https://patentgrep.com/patent/US9520203B2

## CPC

- G11C 29/06: Acceleration testing
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- G11C 2029/1202: {Word line control}
- G11C 2029/2602: {Concurrent test}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a first address input block that receives first information applied from an exterior;
a second address input block that receives second information applied from the exterior;
a normal address buffering block that receives and buffers the first and second information as a corresponding normal address in a normal mode; and
a test signal generation block that receives the first and second information as a test clock and a test code, respectively, in a test mode to generate a test command, a test address and a test data based on the test code and the test clock, in the test mode.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
an internal circuit that performs a predetermined test operation in response to the test command, the test address and the test data in the test mode.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the test signal generation block includes:
a synchronization unit that synchronizes the test code with the test clock to generate a synchronized test code in the test mode; and
a decoding unit that decodes the synchronized test code to generate the test command, the test address and the test data.

### Claim 4 (depends on 3)

The semiconductor memory device of claim 3, wherein the second address input block receives N bit information inputted simultaneously through N address pads as one corresponding normal address in the normal mode, and receives 2N bit information inputted twice in a row through the N address pads as one test code in the test mode, wherein the N is a natural number.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein the synchronization unit synchronizes a first N-bit test code, which is inputted first among the one test code, in parallel with a first edge of the test clock to output an upper test code, and synchronizes a second N-bit test code, which is inputted second among the one test code, in parallel with a second edge of the test clock to output a lower test code.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5, wherein the decoding unit decodes the upper test code to generate the test address and the test data, and decodes the lower test code to generate the test command and the test data.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, wherein the first address input block receives one bit information inputted through one address pad as one corresponding normal address in the normal mode, and receives one bit information inputted toggling at a predetermined period through the address pad as the test clock in the test mode.

### Claim 8 (depends on 3)

The semiconductor memory device of claim 3, wherein the decoding unit enters a test operation section in response to a first predetermined value of the synchronized test code in the test mode, and exits from the test operation section in response to a second predetermined value of the synchronized test code in the test mode,
wherein the decoding unit decodes the synchronized test code and generates the test command, the test address and the test data in the test operation section.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein an operation of the test mode is a wafer burn-in test operation.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein the operation of the test mode is distinguished from an operation of the normal mode based on a signal which is applied based on a setting of a Mode Register Set (MRS) or applied through a predetermined pad.

### Claim 11

A method for operating the semiconductor memory device, comprising:
in a normal mode, receiving first information, applied from an exterior through a plurality of address pads, as a corresponding normal address;
in a test mode, receiving second information, applied from the exterior through a predetermined address pad among the plurality of address pads, as a test clock and receiving third information, applied from the exterior through the other address pads among the plurality of address pads, as a test code;
synchronizing the test code with the test clock to generate a synchronized test code; and
decoding the synchronized test code to generate a test command, a test address and a
test data.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
performing a predetermined test operation in an internal circuit in response to the test command, the test address and the test data.

### Claim 13 (depends on 11)

The method of claim 11, wherein the synchronizing of the test code with the test clock and the generating of the test command, the test address and the test data in response to the synchronized test code includes:
synchronizing the test code with the test clock to generate the synchronized test code; and
decoding the synchronized test code and generating the test command, the test address and the test data.

### Claim 14 (depends on 13)

The method of claim 13, wherein the receiving of the second information and the receiving of the third information includes:
receiving one bit information inputted toggling at a predetermined period through the predetermined address pad as the test clock; and
receiving 2N bit information inputted twice in the row through the other address pads as one test code,
wherein the N is a natural number.

### Claim 15 (depends on 14)

The method of claim 14, wherein the synchronizing of the test code with the test clock includes:
synchronizing a first N-bit test code, which is inputted first among the one test code, with a first edge of the test clock in parallel and outputting an upper test code; and
synchronizing a second N-bit test code, which is inputted second among the one test code, with a second edge of the test clock in parallel and outputting a lower test code.

### Claim 16 (depends on 15)

The method of claim 15, wherein the decoding of the synchronized test code and the generating of the test command, the test address and the test data includes:
decoding the upper test code and generating the test address and the test data; and
decoding the lower test code and generating the test command and the test data.

### Claim 17 (depends on 14)

The method of claim 14, wherein N+1 bit information is inputted simultaneously through the address pads as one corresponding normal address in the receiving of the first information.

### Claim 18 (depends on 13)

The method of claim 13, wherein the decoding of the synchronized test code and the generating of the test command, the test address and the test data includes:
entering a test operation section in response to a first predetermined value of the synchronized test code;
exiting from the test operation section in response to a second predetermined value of the synchronized test code; and
decoding the synchronized test code and generating the test command, the test address and the test data while entering the test operation section.

### Claim 19 (depends on 11)

The method of claim 11, wherein an operation of the test mode is a wafer burn-in test operation.

### Claim 20 (depends on 11)

The method of claim 11, wherein the operation of the test mode is distinguished from an operation of the normal mode in response to a signal which is applied based on a setting of a Mode Register Set (MRS) or is applied through a predetermined pad.