# US 9,520,201 B2 · Nonvolatile memory device comprising page buffer and program verification operation method thereof

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- Number: US 9,520,201 B2
- Document ID: US9520201B2
- Status: Granted
- Kind: B2
- Application number: 14/853,488
- Filed: 2015-09-14
- Published: 2016-01-14
- Granted: 2016-12-13
- Earliest claimed: 2012-12-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dongku Kang; Dae Yeal Lee
- Web page: https://patentgrep.com/patent/US9520201B2

## CPC

- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3481: {Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming}
- G11C 17/06: using diode elements (G11C17/14 takes precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile memory device is provided which includes a page buffer unit. The page buffer unit includes a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data, and a second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data. A set pulse may be applied to both the first A latch and the second B latch, or to both the second A latch and the first B latch. The non-volatile memory device may provide high write performance and may respond within a time out period of a handheld terminal.

## Claims

### Claim 1

A nonvolatile memory device including a page buffer unit, the page buffer unit comprising:
a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data; and
a second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data,
wherein a set pulse is applied to both the first A latch and the second B latch, or to both the second A latch and the first B latch.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the set pulse is simultaneously applied to the first page buffer and second page buffer during a program verify operation.

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein
the first page buffer further comprises a first sensing latch, and
the first page buffer is configured to store the first upper bit data in the first A latch according to data stored in the first sensing latch.

### Claim 4 (depends on 3)

The nonvolatile memory device of claim 3, wherein
the second page buffer further comprises a second sensing latch, and
the second page buffer is configured to store the second lower bit data in the second B latch according to data stored in the second sensing latch.

### Claim 5 (depends on 1)

The nonvolatile memory device of claim 1, wherein each of the first and second upper bit data is a most significant bit (MSB) of multiple bits, and each of the first and second lower bit data is a least significant bit (LSB) of multiple bits.

### Claim 6

A nonvolatile memory device, comprising:
a cell array including a plurality of memory cells;
a first page buffer configured to connect to a first bit line of a first memory cell of the plurality of memory cells, the first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data;
a second page buffer configured to connect to a second bit line of a second memory cell of the plurality of memory cells, the second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data; and
a control logic configured to apply a set pulse to both the first A latch and the second B latch, or to both the second A latch and the first B latch, to set the first and second page buffers to be in a program inhibit state.

### Claim 7 (depends on 6)

The nonvolatile memory device of claim 6, wherein the set pulse is applied to the first page buffer and second page buffer during a program verify operation of the first memory cell and the second memory cell.

### Claim 8 (depends on 6)

The nonvolatile memory device of claim 6, wherein
the first page buffer further comprises a first sensing latch configured to latch data from the first memory cell; and
the second page buffer further comprises a second sensing latch configured to latch data from the second memory cell.

### Claim 9 (depends on 8)

The nonvolatile memory device of claim 8, wherein
the first page buffer is configured to store the first upper bit data in the first A latch according to data stored in the first sensing latch; and
the second page buffer is configured to store the second lower bit data in the second B latch according to data stored in the second sensing latch.

### Claim 10 (depends on 8)

The nonvolatile memory device of claim 8, wherein each of the first and second upper bit data is a most significant bit (MSB) of multiple bits, and each of the first and second lower bit data is a least significant bit (LSB) of multiple bits.

### Claim 11 (depends on 10)

The nonvolatile memory device of claim 10, wherein the most significant bit (MSB) of multiple bits to be programmed into the first memory cell is loaded in the first A latch, and the least significant bit (LSB) of multiple bits to be programmed into the second memory cell is loaded in the second B latch.

### Claim 12 (depends on 8)

The nonvolatile memory device of claim 8, further comprising:
a first sensing node is configured to transfer data of the first sensing latch to one of the first A latch and the first B latch; and
a second sensing node is configured to transfer data of the second sensing latch to one of the second A latch and the second B latch.

### Claim 13 (depends on 12)

The nonvolatile memory device of claim 12, wherein each of the first and second page buffers further comprise a pre-charge circuit configured to pre-charge the first sensing node and the second sensing node with a power supply voltage level to transfer data of the first sensing latch or the second sensing latch.

### Claim 14 (depends on 6)

The nonvolatile memory device of claim 6, wherein the plurality of memory cells are formed with a three-dimensional structure.

### Claim 15

A method of operating a nonvolatile memory device including a first page buffer having a first sensing latch, a first sensing node, and a first data latch, and a second page buffer having a second sensing latch, a second sensing node, and a second data latch, the operating method comprising:
developing the first and second sensing nodes according to data stored at the first and second data latches;
setting the first data latch according to a voltage level of the first sensing node in response to a set pulse; and
setting the second data latch according to a voltage level of the second sensing node in response to the set pulse.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
sensing the data stored at the first and second sensing latches from corresponding memory cells for a program verify operation.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first page buffer further includes a third data latch and the second page buffer further includes a fourth data latch, and the operating method further comprising:
storing first target data to be programmed into a first memory cell at the first and third data latches; and
storing second target data to be programmed into a second memory cell at the second and fourth data latches.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first to fourth data latches are maintained at a target state in response to the set pulse, or are set to data corresponding to a program inhibit state in response to the set pulse.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first data latch stores a most significant bit (MSB) to be programmed at a first memory cell, and the second data latch stores a least significant bit (LSB) to be programmed at a second memory cell.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
pre-charging the first sensing node with a power supply voltage level to transfer data of the first sensing latch to the first sensing node; and
pre-charging the second sensing node with the power supply voltage level to transfer data of the second sensing latch to the second sensing node.