# US 9,520,199 B2 · Memory device and reading method thereof

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- Number: US 9,520,199 B2
- Document ID: US9520199B2
- Status: Granted
- Kind: B2
- Application number: 14/692,927
- Filed: 2015-04-22
- Published: 2016-10-27
- Granted: 2016-12-13
- Earliest claimed: 2015-04-22
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Kuo-Pin Chang
- Web page: https://patentgrep.com/patent/US9520199B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device includes: a plurality of conductive stacked structures including at least a string select line, a plurality of word lines and at least a ground select line; a plurality of memory cells formed in the conductive stacked structures; a plurality of bit lines, formed on the conductive stacked structures; and at least an odd common source line and at least an even common source line, formed on the conductive stacked structures. The odd common source line is coupled to a plurality of odd bit lines of the bit lines. The even common source line is coupled to a plurality of even bit lines of the bit lines.

## Claims

### Claim 1

A memory device including:
a plurality of conductive stack structures, including at least a string select line, a plurality of word lines, at least an odd ground select line and at least an even ground select line;
a plurality of memory cells, formed in the conductive stack structures;
a plurality of bit lines, formed on the conductive stack structures; and
at least a common source line, formed on the conductive stack structures,
wherein the odd ground select line is coupled to a plurality of odd bit lines of the bit lines, and the even ground select line is coupled to a plurality of even bit lines of the bit lines.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein
a string current from any odd bit line of the odd bit lines flow through a corresponding conductive stack structure of the conductive stack structures into the common source line; and
another string current from any even bit line of the even bit lines flow through another corresponding conductive stack structure of the conductive stack structures into the common source line.

### Claim 3 (depends on 1)

The memory device according to claim 1, wherein
the string select line and a first word line group of the word lines are stacked as a first conductive stack structure of the conductive stack structures; and
the ground select line and a second word line group of the word lines are stacked as a second conductive stack structure of the conductive stack structures.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein
the memory cells are formed on a plurality of sidewalls of the conductive stack structures; and
the odd ground select line is electrically isolated from the even ground select line.