# US 9,520,196 B1 · Voltage switch circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,196 B1 - Document ID: US9520196B1 - Status: Granted - Kind: B1 - Application number: 15/152,047 - Filed: 2016-05-11 - Granted: 2016-12-13 - Earliest claimed: 2016-01-19 - Assignees: eMemory Technology Inc. - Applicants: eMemory Technology Inc. - Inventors: Chen-Hao Po - Web page: https://patentgrep.com/patent/US9520196B1 ## CPC - G11C 16/30: Power supply circuits - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 8/10: Decoders - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - G11C 16/0458: {comprising two or more independent floating gates which store independent data} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/12: Programming voltage switching circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates - H10B 41/10: characterised by the top-view layout - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 41/40: characterised by the peripheral circuit region - H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell - H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 89/10: Integrated device layouts - H10W 20/43: Layouts of interconnections - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A voltage switch circuit is connected to a memory cell of a non-volatile memory. When the non-volatile memory is in a program mode and the memory cell is a selected memory cell, two output terminals provide a high voltage. When the non-volatile memory is in the program mode and the memory cell is a non-selected memory cell, the two output terminals provide a medium voltage and a ground voltage. When the non-volatile memory is in an erase mode and the memory cell is the selected memory cell, the two output terminals provide the high voltage and the ground voltage. When the non-volatile memory is in the erase mode and the memory cell is the non-selected memory cell, the two output terminals provide the ground voltage. When the non-volatile memory is in a read mode, the two output terminals provide a read voltage. ## Claims ### Claim 1 A voltage switch circuit connected to a memory cell of a non-volatile memory, the voltage switch circuit comprising: a first transistor, wherein a source terminal of the first transistor is connected to a first voltage source, and a gate terminal of the first transistor is connected to a node a1; a second transistor, wherein a source terminal of the second transistor is connected to the first voltage source, and a gate terminal of the second transistor is connected to a node b1; a third transistor, wherein a source terminal of the third transistor is connected to a drain terminal of the first transistor, a gate terminal of the third transistor receives an enabling signal, and a drain terminal of the third transistor is connected to a node a2; a fourth transistor, wherein a source terminal of the fourth transistor is connected to a drain terminal of the second transistor, a gate terminal of the fourth transistor receives the enabling signal, and a drain terminal of the fourth transistor is connected to a node b2; a fifth transistor, wherein a source terminal of the fifth transistor is connected to the node a2, a gate terminal of the fifth transistor is connected to a second voltage source, and a drain terminal of the fifth transistor is connected to a first output terminal; a sixth transistor, wherein a source terminal of the sixth transistor is connected to the node b2, a gate terminal of the sixth transistor is connected to a third voltage source, and a drain terminal of the sixth transistor is connected to a second output terminal; a seventh transistor, wherein a source terminal of the seventh transistor is connected to a fourth voltage source, a gate terminal of the seventh transistor is connected to the second output terminal, and a drain terminal of the seventh transistor is connected to the node a2; a first control circuit connected to the node a1, the node b1 and the node a2; and a second control circuit connected to the first output terminal and the second output terminal, wherein in a program mode and an erase mode of the non-volatile memory, the first voltage source provides a high voltage, the second voltage source provides a medium voltage or a ground voltage, the third voltage source provides a control voltage, and the fourth voltage source provides the medium voltage, wherein in a read mode of the non-volatile memory, all of the first voltage source, the second voltage source and the third voltage source provide a high logic level voltage, and the fourth voltage source provides the ground voltage, wherein the high voltage is higher than the medium voltage, the medium voltage is higher than the high logic level voltage, and the control voltage is in a range between the medium voltage and the high voltage. ### Claim 2 (depends on 1) The voltage switch circuit as claimed in claim 1, wherein the first control circuit comprises: an eighth transistor, wherein a source terminal of the eighth transistor receives a bias voltage, a gate terminal of the eighth transistor receives a first control signal, and a drain terminal of the eighth transistor is connected to the node a1; a ninth transistor, wherein a source terminal of the ninth transistor is connected to the first voltage source, a gate terminal of the ninth transistor receives a second control signal, and a drain terminal of the ninth transistor is connected to the node a1; a tenth transistor, wherein a source terminal of the tenth transistor receives the bias voltage, a gate terminal of the tenth transistor receives a third control signal, and a drain terminal of the tenth transistor is connected to the node b1; and an eleventh transistor, wherein a source terminal of the eleventh transistor is connected to the node a2, a gate terminal of the eleventh transistor receives a fourth control signal, and a drain terminal of the eleventh transistor is connected to the node b1, wherein the high voltage is higher than the bias voltage. ### Claim 3 (depends on 2) The voltage switch circuit as claimed in claim 2, wherein when the non-volatile memory is in the program mode and the memory cell is a selected memory cell, the first transistor and the second transistor are turned on according to the bias voltage, the third transistor and the fourth transistor are turned on according to an enabling voltage of the enabling signal, the fifth transistor is turned on according to the medium voltage, the sixth transistor is turned on according to the control voltage, and the second control circuit is inactivated, so that the high voltage is outputted from the first output terminal and the second output terminal, wherein the enabling voltage is lower than the high voltage. ### Claim 4 (depends on 2) The voltage switch circuit as claimed in claim 2, wherein when the non-volatile memory is in the program mode and the memory cell is a non-selected memory cell, the first transistor and the second transistor are turned on according to the bias voltage, the third transistor and the fourth transistor are turned off according to a disabling voltage of the enabling signal, the fifth transistor is turned on according to the ground voltage, the sixth transistor is turned off according to the control voltage, and the second control circuit provides a low logic level voltage to the second output terminal, so that the seventh transistor is turned on and the medium voltage is outputted from the first output terminal, wherein the disabling voltage is lower than or equal to the high voltage. ### Claim 5 (depends on 2) The voltage switch circuit as claimed in claim 2, wherein when the non-volatile memory is in the erase mode and the memory cell is a selected memory cell, the first transistor is turned off according to the high voltage, the second transistor is turned on, the third transistor and the fourth transistor are turned on according to an enabling voltage of the enabling signal, the fifth transistor is turned off according to the medium voltage, the sixth transistor is turned on according to the control voltage, and the second control circuit provides a low logic level voltage to the first output terminal, so that the low logic level voltage is outputted from the first output terminal and the high voltage is outputted from the second output terminal, wherein the enabling voltage is lower than the high voltage. ### Claim 6 (depends on 2) The voltage switch circuit as claimed in claim 2, wherein when the non-volatile memory is in the erase mode and the memory cell is a non-selected memory cell, the first transistor is turned off according to the high voltage, the second transistor is turned on, the third transistor and the fourth transistor are turned off according to a disabling voltage of the enabling signal, the fifth transistor is turned off according to the medium voltage, the sixth transistor is turned off according to the control voltage, and the second control circuit provides a low logic level voltage to the first output terminal and the second output terminal, so that the low logic level voltage is outputted from the first output terminal and the second output terminal and the seventh transistor is turned on, wherein the disabling voltage is lower than or equal to the high voltage. ### Claim 7 (depends on 2) The voltage switch circuit as claimed in claim 2, wherein when the non-volatile memory is in the read mode, the first transistor and the second transistor are turned off, the enabling signal has the high logic level voltage, the third transistor and the fourth transistor are turned off according to the enabling signal, the fifth transistor and the sixth transistor are turned off according to the high logic level voltage, and the second control circuit provides a read voltage to the first output terminal and the second output terminal, so that the read voltage is outputted from the first output terminal and the second output terminal. ### Claim 8 (depends on 1) The voltage switch circuit as claimed in claim 1, wherein the second control circuit comprises: a twelfth transistor, wherein a drain terminal of the twelfth transistor is connected to the first output terminal, a gate terminal of the twelfth transistor receives the high logic level voltage, and a source terminal of the twelfth transistor is connected to a node a3; a thirteen transistor, wherein a drain terminal of the thirteen transistor is connected to the second output terminal, a gate terminal of the thirteen transistor receives the high logic level voltage, and a source terminal of the thirteen transistor is connected to a node b3; a fourteenth transistor, wherein a drain terminal of the fourteenth transistor is connected to the node a3, a gate terminal of the fourteenth transistor receives an erase signal, and a source terminal of the fourteenth transistor receives an inverted erase signal; a fifteenth transistor, wherein a drain terminal of the fifteenth transistor is connected to the node a3, a gate terminal of the fifteenth transistor receives a read signal, and a source terminal of the fifteenth transistor receives a read voltage; a sixteenth transistor, wherein a drain terminal of the sixteenth transistor is connected to the node b3, a source terminal of the sixteenth transistor receives a first input signal, and a gate terminal of the sixteenth transistor receives an inverted first input signal; and a seventeenth transistor, wherein a drain terminal of the seventeenth transistor is connected to the node b3, a gate terminal of the seventeenth transistor receives the read signal, and a source terminal of the seventeenth transistor receives the read voltage. ### Claim 9 (depends on 8) The voltage switch circuit as claimed in claim 8, wherein when the non-volatile memory is in the program mode and the memory cell is a selected memory cell, the first input signal has the high logic level voltage, and the erase signal and the read signal have a low logic level voltage, so that the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are turned off. ### Claim 10 (depends on 8) The voltage switch circuit as claimed in claim 8, wherein when the non-volatile memory is in the program mode and the memory cell is a non-selected memory cell, the first input signal, the erase signal and the read signal have a low logic level voltage, so that the sixteenth transistor is turned on and the fourteenth transistor, the fifteenth transistor and the seventeenth transistor are turned off. ### Claim 11 (depends on 8) The voltage switch circuit as claimed in claim 8, wherein when the non-volatile memory is in the erase mode and the memory cell is a selected memory cell, the first input signal and the erase signal have the high logic level voltage, and the read signal have a low logic level voltage, so that the fourteenth transistor is turned on, and the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are turned off. ### Claim 12 (depends on 8) The voltage switch circuit as claimed in claim 8, wherein when the non-volatile memory is in the erase mode and the memory cell is a non-selected memory cell, the erase signal have the high logic level voltage, and the first input signal and the read signal have a low logic level voltage, so that the fourteenth transistor and the sixteenth transistor are turned on and the fifteenth transistor and the seventeenth transistor are turned off. ### Claim 13 (depends on 8) The voltage switch circuit as claimed in claim 8, wherein when the non-volatile memory is in the read mode, the first input signal has the high logic level voltage, and the erase signal and the read signal have a low logic level voltage, so that the fifteenth transistor and the seventeenth transistor and turned on and the fourteenth transistor and the sixteenth transistor are turned off. ### Claim 14 (depends on 1) The voltage switch circuit as claimed in claim 1, wherein the first control circuit comprises: an eighth transistor, wherein a source terminal of the eighth transistor receives a bias voltage, a gate terminal of the eighth transistor receives a first control signal, and a drain terminal of the eighth transistor is connected to the node a1; a ninth transistor, wherein a source terminal of the ninth transistor is connected to the node b2, a gate terminal of the ninth transistor receives a second control signal, and a drain terminal of the ninth transistor is connected to the node a1; a tenth transistor, wherein a source terminal of the tenth transistor receives the bias voltage, a gate terminal of the tenth transistor receives a third control signal, and a drain terminal of the tenth transistor is connected to the node b1; and an eleventh transistor, wherein a source terminal of the eleventh transistor is connected to the node a2, a gate terminal of the eleventh transistor receives a fourth control signal, and a drain terminal of the eleventh transistor is connected to the node b1, wherein the high voltage is higher than the bias voltage. ### Claim 15 (depends on 14) The voltage switch circuit as claimed in claim 14, wherein when the non-volatile memory is in the program mode and the memory cell is a selected memory cell, the first transistor and the second transistor are turned on according to the bias voltage, the third transistor and the fourth transistor are turned on according to an enabling voltage of the enabling signal, the fifth transistor is turned on according to the medium voltage, the sixth transistor is turned on according to the control voltage, and the second control circuit is inactivated, so that the high voltage is outputted from the first output terminal and the second output terminal, wherein the enabling voltage is lower than the high voltage. ### Claim 16 (depends on 14) The voltage switch circuit as claimed in claim 14, wherein when the non-volatile memory is in the program mode and the memory cell is a non-selected memory cell, the first transistor and the second transistor are turned on according to the bias voltage, the third transistor and the fourth transistor are turned off according to a disabling voltage of the enabling signal, the fifth transistor is turned on according to the ground voltage, the sixth transistor is turned off according to the control voltage, and the second control circuit provides a low logic level voltage to the second output terminal, so that the seventh transistor is turned on and the medium voltage is outputted from the first output terminal, wherein the disabling voltage is lower than or equal to the high voltage. ### Claim 17 (depends on 14) The voltage switch circuit as claimed in claim 14, wherein when the non-volatile memory is in the erase mode and the memory cell is a selected memory cell, the first transistor is turned off according to the high voltage, the second transistor is turned on, the third transistor and the fourth transistor are turned on according to an enabling voltage of the enabling signal, the fifth transistor is turned off according to the medium voltage, the sixth transistor is turned on according to the control voltage, and the second control circuit provides a low logic level voltage to the first output terminal, so that the low logic level voltage is outputted from the first output terminal and the high voltage is outputted from the second output terminal, wherein the enabling voltage is lower than the high voltage. ### Claim 18 (depends on 14) The voltage switch circuit as claimed in claim 14, wherein when the non-volatile memory is in the erase mode and the memory cell is a non-selected memory cell, the first transistor is turned off, the second transistor is turned on, the third transistor and the fourth transistor are turned off according to a disabling voltage of the enabling signal, the fifth transistor is turned off according to the medium voltage, the sixth transistor is turned off according to the control voltage, and the second control circuit provides a low logic level voltage to the first output terminal and the second output terminal, so that the low logic level voltage is outputted from the first output terminal and the second output terminal and the seventh transistor is turned on, wherein the disabling voltage is lower than or equal to the high voltage. ### Claim 19 (depends on 14) The voltage switch circuit as claimed in claim 14, wherein when the non-volatile memory is in the read mode, the first transistor and the second transistor are turned off, the enabling signal has the high logic level voltage, the third transistor and the fourth transistor are turned off according to the enabling signal, the fifth transistor and the sixth transistor are turned off according to the high logic level voltage, and the second control circuit provides a read voltage to the first output terminal and the second output terminal, so that the read voltage is outputted from the first output terminal and the second output terminal.