# US 9,520,195 B2 · Sensing amplifier utilizing bit line clamping devices and sensing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,195 B2 - Document ID: US9520195B2 - Status: Granted - Kind: B2 - Application number: 14/049,257 - Filed: 2013-10-09 - Published: 2015-04-09 - Granted: 2016-12-13 - Earliest claimed: 2013-10-09 - Assignees: Macronix International Co., Ltd. - Applicants: Macronix International Co., Ltd. - Inventors: Chung-Kuang Chen - Web page: https://patentgrep.com/patent/US9520195B2 ## CPC - G11C 16/06: Auxiliary circuits, e.g. for writing into memory - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/067: {Single-ended amplifiers} - G11C 7/08: Control thereof - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A sensing amplifier comprising a clamp circuit is provided. The clamp circuit is coupled between a first node and a second node. The clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively, and a sensing current from the memory cell flows into the second node via the first node during a sensing time period. ## Claims ### Claim 1 A sensing amplifier, for sensing data stored in a memory cell of a memory string of which one end is coupled to a third node and another end is coupled to a common source line, comprising: a clamp circuit coupled between a first node and a second node, wherein the clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively, and an isolating transistor, coupled between the third node and the first node; wherein the voltage level of the third node is set to be less than the voltage level of the common source line in a bias setup time period, and the first P-type transistor accordingly clamps the voltage level of the first node to be higher than the voltage level of the second node, such that a sensing current from the memory cell flows into the second node via the first node during a sensing time period subsequent to the bias setup time period. ### Claim 2 (depends on 1) The sensing amplifier according to claim 1, wherein the clamp circuit further comprises: a second P-type transistor having a first terminal, a second terminal and a control terminal receiving a second bias signal, wherein the first terminal and the second terminal of the second P-type transistor are coupled to the second terminal of the first P-type transistor and the second node, respectively. ### Claim 3 (depends on 2) The sensing amplifier according to claim 2, wherein the clamp circuit further comprises a third P-type transistor coupled to the second terminal of the first P-type transistor and controlled by a third bias signal. ### Claim 4 (depends on 3) The sensing amplifier according to claim 3, wherein the voltage level of the first bias signal is higher than the voltage level of the third bias signal, and the voltage level of the third bias signal is higher than the voltage level of the second bias signal. ### Claim 5 (depends on 3) The sensing amplifier according to claim 3, wherein the clamp circuit further comprises a limiting transistor coupled to the third P-type transistor and controlled by the voltage of the second node. ### Claim 6 (depends on 5) The sensing amplifier according to claim 5, wherein the voltage level of the first bias signal is higher than the voltage level of the second bias signal, the voltage level of the second bias signal is substantially equal to the voltage level of the third bias signal. ### Claim 7 (depends on 1) The sensing amplifier according to claim 1, further comprises a pre-charging and sensing circuit having a sensing capacitor, wherein one terminal of the sensing capacitor is coupled to the second node, and the other terminal of the sensing capacitor receives a clock signal, wherein the voltage level of the clock signal is pulled low during the sensing time period. ### Claim 8 (depends on 7) The sensing amplifier according to claim 7, further comprises: a latch, for latching a control voltage; and a transistor having a first terminal, a second terminal and a control terminal receiving a transmitting control signal, the first terminal and the second terminal of the transistor being coupled to the second node and the latch, respectively; wherein the transmitting control signal is enabled during the bias setup time period, so that the control voltage is transmitted to the second node. ### Claim 9 (depends on 8) The sensing amplifier according to claim 8, wherein the control voltage is a ground voltage level. ### Claim 10 (depends on 9) The sensing amplifier according to claim 9, wherein the transmitting control signal is disabled to turn off the transistor during the sensing time period. ### Claim 11 A sensing method, for sensing data stored in a memory cell of a memory string of which one end is coupled to a third node and another end is coupled to a common source line, the sensing method comprising: providing a sensing amplifier comprising a clamp circuit, the clamp circuit being coupled between a first node and a second node; providing a first bias signal to a control terminal of a first P-type transistor of the clamp circuit, wherein the first terminal and the second terminal of the first P-type transistor are coupled to the first and second nodes, respectively, providing an isolating transistor coupled between the third node and the first node; and setting the voltage level of the third node to be less than the voltage level of the common source line in a bias setup time period, and accordingly clamping, by the first P-type transistor, the voltage level of the first node to be higher than the voltage level of the second node, such that a sensing current from the memory cell flows into the second node via the first node during a sensing time period subsequent to the bias setup time period. ### Claim 12 (depends on 11) The sensing method according to claim 11, wherein the clamp circuit further comprises a second P-type transistor, the sensing method further comprises: providing a second bias signal to a control terminal of the second P-type transistor of the clamp circuit, wherein a first terminal and a second terminal of the second P-type transistor are coupled to the second terminal of the first P-type transistor and the second node, respectively. ### Claim 13 (depends on 12) The sensing method according to claim 12, wherein the clamp circuit further comprises a third P-type transistor, the sensing method further comprises: proving a third bias signal to a control terminal of the third P-type transistor of the clamp circuit, wherein the third P-type transistor is coupled to the second terminal of the first P-type transistor. ### Claim 14 (depends on 13) The sensing method according to claim 13, wherein the voltage level of the first bias signal is higher than the voltage level of the third bias signal, and the voltage level of the third bias signal is higher than the voltage level of the second bias signal. ### Claim 15 (depends on 13) The sensing method according to claim 13, wherein the clamp circuit further comprises a limiting transistor, the sensing method further comprises: providing the voltage of the second node to a control terminal of the limiting transistor of the clamp circuit, wherein the limiting transistor is coupled to the third P-type transistor. ### Claim 16 (depends on 15) The sensing method according to claim 15, wherein the voltage level of the first bias signal is higher than the voltage level of the second bias signal, and the voltage level of the second bias signal is substantially equal to the voltage level of the third bias signal. ### Claim 17 (depends on 11) The sensing method according to claim 11, wherein the sensing amplifier further comprises a pre-charging and sensing circuit including a sensing capacitor, one terminal of the sensing capacitor is coupled to the second node, and the other terminal of the sensing capacitor receives a clock signal, the sensing method further comprise: pulling the voltage level of the clock signal low in the beginning of the sensing time period. ### Claim 18 (depends on 17) The sensing method according to claim 17, wherein the pre-charging and sensing circuit further comprises a latch and a transistor, a first terminal and a second terminal of the transistor are coupled to the second node and the latch, respectively, the sensing method further comprise: outputting a control voltage with the latch; and providing a transmitting control signal to a control terminal of the transistor, and enabling the transmitting control signal to transmit the control voltage to the second node during the bias setup time period. ### Claim 19 (depends on 18) The sensing method according to claim 18, wherein the control voltage is a ground voltage level. ### Claim 20 (depends on 19) The sensing method according to claim 19, further comprising: disabling the transmitting control signal to turn off the transistor during the sensing time period. ### Claim 21 A sensing amplifier, for sensing data stored in a memory cell, comprising: a clamp circuit coupled between a first node and a second node, wherein the clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively; an isolating transistor, coupled between the first node and a third node coupled to a memory string including the memory cell; and a pre-charging and sensing circuit having a sensing capacitor, wherein one terminal of the sensing capacitor is coupled to the second node, and the other terminal of the sensing capacitor receives a clock signal, wherein the voltage level of the clock signal is pulled low during the sensing time period; wherein the voltage level of the third node is set to be less than the voltage level of the common source line in a bias setup time period, and the first P-type transistor accordingly clamps the voltage level of the first node to be higher than the voltage level of the second node, such that a sensing current from the memory cell flows into the second node via the first node during a sensing time period subsequent to the bias setup time period. ### Claim 22 (depends on 21) The sensing amplifier according to claim 21, wherein the clamp circuit further comprises: a second P-type transistor having a first terminal, a second terminal and a control terminal receiving a second bias signal, wherein the first terminal and the second terminal of the second P-type transistor are coupled to the second terminal of the first P-type transistor and the second node, respectively. ### Claim 23 (depends on 22) The sensing amplifier according to claim 22, wherein the clamp circuit further comprises a third P-type transistor coupled to the second terminal of the first P-type transistor and controlled by a third bias signal. ### Claim 24 (depends on 23) The sensing amplifier according to claim 23, wherein the voltage level of the first bias signal is higher than the voltage level of the third bias signal, and the voltage level of the third bias signal is higher than the voltage level of the second bias signal. ### Claim 25 (depends on 23) The sensing amplifier according to claim 23, wherein the clamp circuit further comprises a limiting transistor coupled to the third P-type transistor and controlled by the voltage of the second node.