# US 9,520,187 B2 · Electric device having wire contacts coupled to stack structures with variable resistance elements

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- Number: US 9,520,187 B2
- Document ID: US9520187B2
- Status: Granted
- Kind: B2
- Application number: 14/867,894
- Filed: 2015-09-28
- Published: 2016-01-21
- Granted: 2016-12-13
- Earliest claimed: 2013-03-28
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jae-Yun Yi; Sung-Woong Chung; Seok-Pyo Song
- Web page: https://patentgrep.com/patent/US9520187B2

## CPC

- G11C 13/0026: {Bit-line or column circuits}
- G06F 13/1673: {using buffers}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 13/0028: {Word-line or row circuits}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10D 89/10: Integrated device layouts
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

## Claims

### Claim 1

An electronic device comprising a semiconductor memory, the semiconductor memory including:
a mat region configured to include a plurality of memory cells coupled with first wires; and
a switching region configured to control coupling between the first wires and an external region in transfer of data stored in the memory cells,
wherein the mat region comprises:
first active regions formed in a substrate, extended in a second direction, and arranged in a first direction crossing the second direction;
a first gate extended in the first direction across the first active regions;
stack structures respectively disposed over the first active regions on a first side of the first gate, each stack structure including a first lower contact, a variable resistance element, and a first upper contact; and
wire contacts disposed over every first active regions on a second side of the first gate, and
fourth wires, wherein the first wires are coupled with one of the stack structures and the wire contacts and extended in the second direction, and the fourth wires coupled with the other of the stack structures and the wire contacts and extended in the second direction.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the switching region includes:
second active regions formed in the substrate, arranged in the first direction and extended in the second direction;
second gates extended in the first direction across the second active regions;
second lower contacts disposed over the substrate on both sides of each second gate, each second lower contact configured to couple the second active regions arranged in the first direction;
second upper contacts disposed over the second lower contacts, each second upper contact overlapping with a corresponding second active region on a first side of each second gate and overlapping with every second active regions on a second side of each second gate;
second wires coupled with the second upper contacts on the first side of each second gate and the first wires and extended in the second direction; and
third wires coupled with the second upper contacts on the second side of each second gate and an external region and extended in the second direction.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein the first and the second active regions, the first and the second gates, the first and the second lower contacts, the first to the third upper contacts, and the first to the fourth wires are placed at the same height.

### Claim 4 (depends on 2)

The electronic device of claim 2, wherein:
the switching region is disposed on at least one side of the mat region in the second direction, and
the electronic device further comprises:
a first driver disposed on at least one side of the mat region in the first direction, and coupled with the first gate to control the first gate; and
a second driver placed in a region defined by the switching region and the first driver, and coupled with the second gate to control the second gate.

### Claim 5 (depends on 2)

The electronic device of claim 2, wherein a number of the first wires, a number of the second active regions, a number of the second gates, a number of the second wires, a number of the third wires and a number of the first active regions are same.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the mat region and the switching region share a well formed in the substrate.

### Claim 7 (depends on 1)

The electronic device according to claim 1, further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

### Claim 8 (depends on 1)

The electronic device according to claim 1, further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory is part of the cache memory unit in the processor.

### Claim 9 (depends on 1)

The electronic device according to claim 1, further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

### Claim 10 (depends on 1)

The electronic device according to claim 1, further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

### Claim 11

An electronic device comprising semiconductor memory, wherein the semiconductor memory includes:
a mat region configured to comprise a plurality of memory cells and first wires coupled with the plurality of memory cells; and
a switching region configured to control coupling between the each of the first wires and an external region,
wherein the switching region comprises:
second wires coupled with the respective first wires and extended in a second direction;
third wires configured to correspond to the respective second wires, extended in the second direction, and coupled with the external region;
second gate lines configured to correspond to the respective first wires and extended in a first direction crossing the second direction; and
switching transistors configured to have gates coupled with each of the second gate lines and arranged in the first direction,
wherein first nodes of the switching transistors are coupled together and coupled with a corresponding second wire of the second wires, and second nodes of the switching transistors are coupled with all the N third wires.

### Claim 12 (depends on 11)

The electronic device of claim 11, wherein
each of the plurality of memory cells comprises a variable resistance element and a selection transistor, and
the mat region includes the first wire extended in the first direction and coupled with a first end of the memory cell, a fourth wire extended in the first direction and coupled with a second end of the memory cell, and a first gate line coupled with a gate of the selection transistor and extended in the first direction.

### Claim 13 (depends on 12)

The electronic device of claim 12, wherein:
the switching region is disposed on at least one side of the mat region in the second direction, and
the electronic device further comprises:
a first driver disposed on at least one side of the mat region in the first direction, coupled with the first gate line, and configured to control the first gate line; and
a second driver placed in a region defined by the switching region and the first driver, coupled with the second gate line, and configured to control the second gate line.

### Claim 14 (depends on 11)

The electronic device of claim 11, wherein:
the first wires are included in a wire group, the mat region includes wire groups,
the switching region comprises small switching regions configured to correspond to the respective wire groups and arranged in the first direction, and
the second gate line is shared in the small switching regions.

### Claim 15 (depends on 14)

The electronic device of claim 14, wherein the number of wire groups of the mat region are coupled with different external regions through the respective small switching region.

### Claim 16 (depends on 11)

The electronic device of claim 11, wherein a number of the first wires, a number of the second wires, a number of the third wires, a number of the second gate lines, and a number of the switching transistors coupled to each second gate line are same.

### Claim 17 (depends on 11)

The electronic device according to claim 11, further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

### Claim 18 (depends on 11)

The electronic device according to claim 11, further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory is part of the cache memory unit in the processor.

### Claim 19 (depends on 11)

The electronic device according to claim 11, further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

### Claim 20 (depends on 11)

The electronic device according to claim 11, further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.