# US 9,520,184 B2 · Method for writing in-system programming code into flash memory for better noise margin

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- Number: US 9,520,184 B2
- Document ID: US9520184B2
- Status: Granted
- Kind: B2
- Application number: 14/615,435
- Filed: 2015-02-06
- Published: 2015-08-13
- Granted: 2016-12-13
- Earliest claimed: 2014-02-10
- Assignees: Silicon Motion, Inc.
- Applicants: Silicon Motion Inc.
- Inventors: Tsung-Chieh Yang
- Web page: https://patentgrep.com/patent/US9520184B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention provides a method for writing a data into a flash memory, wherein the flash memory is a Triple-Level Cell flash memory, and each storage unit of the flash memory is implemented by a floating-gate transistor and each storage unit supports eight write voltage levels, and the method includes: adjusting the data bit by bit to generate a pseudo-random bit sequence; and writing the pseudo-random bit sequence into the flash memory with only two specific voltage levels of the eight write voltage levels.

## Claims

### Claim 1

A memory device, which comprising:
a flash memory, wherein the flash memory is a Triple-Level Cell flash memory, each storage unit of the flash memory is implemented by a floating-gate transistor and each storage unit supports eight write voltage levels; and
a memory controller arranged to access the flash memory;
wherein before the first time the memory controller reads the flash memory, data in the flash memory is stored with only two specific voltage levels of the eight write voltage levels, wherein the data comprises least significant bits (LSBs), central significant bits (CSBs) and most significant bits (MSBs).

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the data is an In-System Programming code.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the eight write voltage levels sequentially are a first voltage level, a second voltage level, a third voltage level, a fourth voltage level, a fifth voltage level, a sixth voltage level, a seventh voltage level, and an eighth voltage level respectively, the MSB, the CSB and the LSB corresponded to the first voltage level are (1, 1, 1) respectively, the MSB, the CSB and the LSB corresponded to the second voltage level are (1, 1, 0) respectively, the MSB, the CSB and the LSB corresponded to the third voltage level are (1, 0, 0) respectively, the MSB, the CSB and the LSB corresponded to the fourth voltage level are (0, 0, 0) respectively, the MSB, the CSB and the LSB corresponded to the fifth voltage level are (0, 1, 0) respectively, the MSB, the CSB and the LSB corresponded to the sixth voltage level are (0, 1, 1) respectively, the MSB, the CSB and the LSB corresponded to the seventh voltage level are (0, 0, 1) respectively, the MSB, the CSB and the LSB corresponded to the eighth voltage level are (1, 0, 1) respectively, and the two specific voltage levels are the first voltage level and the fourth voltage level respectively.

### Claim 4

A flash memory, wherein the flash memory is a Triple-Level Cell flash memory, each storage unit of the flash memory is implemented by a floating-gate transistor and each storage unit supports eight write voltage levels; wherein before the first time the flash memory is read by a memory controller, data in the flash memory is stored with only two specific voltage levels of the eight write voltage levels, wherein the data comprises least significant bits (LSBs), central significant bits (CSBs) and most significant bits (MSBs).

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the data is an In-System Programming code.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein the eight write voltage levels sequentially are a first voltage level, a second voltage level, a third voltage level, a fourth voltage level, a fifth voltage level, a sixth voltage level, a seventh voltage level, and an eighth voltage level respectively, the MSB, the CSB and the LSB corresponded to the first voltage level are (1, 1, 1) respectively, the MSB, the CSB and the LSB corresponded to the second voltage level are (1, 1, 0) respectively, the MSB, the CSB and the LSB corresponded to the third voltage level are (1, 0, 0) respectively, the MSB, the CSB and the LSB corresponded to the fourth voltage level are (0, 0, 0) respectively, the MSB, the CSB and the LSB corresponded to the fifth voltage level are (0, 1, 0) respectively, the MSB, the CSB and the LSB corresponded to the sixth voltage level are (0, 1, 1) respectively, the MSB, the CSB and the LSB corresponded to the seventh voltage level are (0, 0, 1) respectively, the MSB, the CSB and the LSB corresponded to the eighth voltage level are (1, 0, 1) respectively, and the two specific voltage levels are the first voltage level and the fourth voltage level respectively.