# US 9,520,183 B2 · Threshold voltage compensation in a memory

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- Number: US 9,520,183 B2
- Document ID: US9520183B2
- Status: Granted
- Kind: B2
- Application number: 14/707,684
- Filed: 2015-05-08
- Published: 2015-08-27
- Granted: 2016-12-13
- Earliest claimed: 2011-08-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Violante Moschiano; Tommaso Vali; Giovanni Naso; Vishal Sarin; William Henry Radke; Theodore T. Pekny
- Web page: https://patentgrep.com/patent/US9520183B2

## CPC

- G11C 11/5621: {using charge storage in a floating gate}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

## Claims

### Claim 1

A method of operating a memory, comprising:
providing an analog ramp signal to a control gate of a memory cell;
converting a value of a digital signal corresponding to the analog ramp signal to a converted digital value; and
providing the converted digital value to a buffer coupled to the memory cell, wherein a difference between the converted digital value and the digital signal value results in a difference in threshold voltage in the memory cell.

### Claim 2 (depends on 1)

The method of operating a memory of claim 1, wherein the digital signal corresponding to the analog ramp signal is coupled to a digital-to-analog converter coupled to a select line to provide the analog ramp signal to the control gate of the memory cell.

### Claim 3 (depends on 1)

The method of operating a memory of claim 1, wherein there is a greater voltage difference between high threshold voltage data states than low threshold voltage data states in the memory cell.

### Claim 4 (depends on 1)

The method of operating a memory of claim 1, wherein providing the converted digital value to a buffer comprises providing the converted digital value to a buffer operable to be selectively coupled to the memory cell via a sense amplifier.

### Claim 5 (depends on 1)

The method of operating a memory of claim 1, wherein converting a value of a digital signal comprises converting the value of the digital signal using a data structure.

### Claim 6 (depends on 1)

The method of operating a memory of claim 1, wherein the memory comprises a memory chip, a memory card, a smart phone, or a solid state storage device.

### Claim 7 (depends on 1)

The method of operating a memory of claim 1, wherein converting a value of a digital signal comprises converting the value of the digital signal using a look up table.

### Claim 8 (depends on 1)

The method of operating a memory of claim 1, wherein a converted digital value corresponds to a target threshold voltage of a data state, and wherein a target threshold voltage of each data state is a specified constant multiplied by a target threshold voltage of its next lower data state.

### Claim 9 (depends on 1)

The method of operating a memory of claim 1, including incrementing a word line digital to analog converter (DAC) to produce the analog ramp signal, and wherein providing an analog ramp signal includes providing the analog ramp signal to a control gate of a multi-level memory cell.

### Claim 10 (depends on 1)

The method of operating a memory of claim 1, wherein providing the converted digital value to a buffer includes providing the converted digital value to a page buffer DAC coupled to the memory cell.

### Claim 11

A memory, comprising:
a memory cell having a control gate operable to receive an analog ramp signal;
conversion logic operable to receive a digital signal corresponding to the analog ramp signal, wherein the conversion logic is operable to convert a value of the digital signal to a converted digital value; and
a buffer operable to receive the converted digital value, the buffer further operable to be selectively coupled to the memory cell, wherein the difference between the converted digital value and the digital signal value results in a difference in threshold voltage in the memory cell.

### Claim 12 (depends on 11)

The memory of claim 11, wherein the digital signal corresponding to the analog ramp signal is coupled to a digital-to-analog converter coupled to a select line to provide the analog ramp signal to the control gate of the memory cell.

### Claim 13 (depends on 11)

The memory of claim 11, further comprising a sense amplifier coupled to the buffer and operable to be selectively coupled to the memory cell.

### Claim 14 (depends on 11)

The memory of claim 11, wherein the conversion logic comprises a buffer having a data structure.

### Claim 15 (depends on 11)

The memory of claim 11, wherein the conversion logic is operable to provide a greater voltage difference between high threshold voltage data states than low threshold voltage data states in the memory cell.

### Claim 16 (depends on 11)

The memory of claim 11, wherein the memory comprises a memory chip, a memory controller, a memory card, or a solid state storage device.

### Claim 17 (depends on 11)

The memory of claim 11, wherein the conversion logic comprises a buffer having a look up table.

### Claim 18 (depends on 11)

The memory of claim 11, wherein a converted digital value corresponds to a target threshold voltage of a data state, and wherein the conversion logic is operable to provide converted digital values so that a target threshold voltage of each data state is a specified constant multiplied by a target threshold voltage of its next lower data state.

### Claim 19 (depends on 11)

The memory of claim 11, including a word line digital to analog converter (DAC) operable to produce the analog ramp signal, wherein the memory cell is a multi-level memory cell operable to receive the analog amp signal from the word line DAC.

### Claim 20 (depends on 11)

The memory of claim 11, wherein the buffer includes a page buffer DAC coupled to the memory cell.