# US 9,520,173 B1 · Magnetic random access memory (MRAM) and method of operation

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- Number: US 9,520,173 B1
- Document ID: US9520173B1
- Status: Granted
- Kind: B1
- Application number: 15/057,004
- Filed: 2016-02-29
- Granted: 2016-12-13
- Earliest claimed: 2016-02-29
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Freescale Semiconductor, Inc.
- Inventors: Frank K. Baker, Jr.; Michael A. Sadd; Anirban Roy; Bruce L. Morton
- Web page: https://patentgrep.com/patent/US9520173B1

## CPC

- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0042: {Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]}
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2213/74: Array wherein each memory cell has more than one access device
- G11C 2213/79: Array wherein the access device being a transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.

## Claims

### Claim 1

A memory device comprising:
a first memory cell including a first transistor, a second transistor, and a resistive storage element, wherein
during a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element, and
during a write operation, current is conducted through the first and second transistors.

### Claim 2 (depends on 1)

The memory device of claim 1 further comprising:
a sense amplifier;
a second memory cell including a first transistor, a second transistor, and a resistive storage element;
a word line coupled to control gates of the first and second transistors of the first and second memory cells; and
a source line coupled to a second terminal of the resistive storage elements in the first and second memory cells,
wherein the first transistor of the second memory cell is used by the sense amplifier to sense a feedback voltage at the second terminal of the resistive storage element in the first memory cell during the read operation.

### Claim 3 (depends on 2)

The memory device of claim 2 wherein:
the voltage at the first current electrode of the first transistor of the second memory cell is approximately the same as voltage at the second terminal of the resistive storage element of the first memory cell during the read operation.

### Claim 4 (depends on 2)

The memory device of claim 2 wherein:
a first current electrode of the first transistor of the first memory cell is coupled to provide feedback for a third memory cell during a read operation.

### Claim 5 (depends on 1)

The memory device of claim 1 wherein:
the first memory cell is coupled directly adjacent to the second memory cell.

### Claim 6 (depends on 4)

The memory device of claim 4 wherein:
a first current electrode of the second transistor of the second memory cell is coupled to float or to a source voltage during the read operation;
a second current electrode of the first and second transistors of the second memory cell is coupled to the first terminal of the resistive storage element of the second memory cell.

### Claim 7 (depends on 2)

The memory device of claim 2 wherein:
a first current electrode of the second transistor of the first memory cell is coupled to a sense voltage during the read operation;
a second current electrode of the first and second transistors of the first memory cell is coupled to the first terminal of the resistive storage element of the first memory cell.

### Claim 8 (depends on 2)

The memory device of claim 2 wherein:
the resistive storage elements of the first and second memory cells comprise a magnetic tunnel junction.

### Claim 9 (depends on 2)

The memory device of claim 2 wherein:
the feedback voltage at the second terminal of the resistive storage element in the first memory cell is used to adjust a current provided to the first memory cell during the read operation.

### Claim 10 (depends on 1)

The memory device of claim 1 further comprising:
a first capacitor in the sense amplifier, the capacitor is coupled to the feedback voltage at the first terminal of the resistive storage element of the first memory cell, wherein the first capacitor provides a high impedance path for the feedback voltage at the first terminal of the resistive storage element of the first memory cell.

### Claim 11 (depends on 10)

The memory device of claim 10 further comprising:
an amplifier in the sense amplifier, wherein the first capacitor includes a first terminal coupled to a first input to the amplifier and a second terminal coupled to the feedback voltage during the read operation.

### Claim 12 (depends on 11)

The memory device of claim 11 further comprising:
a second capacitor in the sense amplifier, the second capacitor includes a first terminal coupled to a second input of the amplifier and a second terminal coupled to a feedback voltage at the second terminal of the resistive storage element in the first memory cell during the read operation.

### Claim 13

A method of operating a memory device comprising:
providing a sense current through a first transistor of a first memory cell;
sensing a first feedback voltage at a first current electrode of a second transistor in the first memory cell, wherein the first feedback voltage is at a first terminal of a resistive storage element and the first current electrode of the second transistor of the first memory cell is coupled to an input of a sense amplifier;
sensing a second feedback voltage at a first current electrode of a first transistor of a second memory cell, wherein the second feedback voltage is at a second terminal of the resistive storage element and the first current electrode of the first transistor of the second memory cell is coupled to another input of the sense amplifier;
adjusting the sense current through the first memory cell based on the first and second feedback voltages.

### Claim 14 (depends on 13)

The method of claim 13 wherein the sense current is adjusted during a read operation.

### Claim 15 (depends on 13)

The method of claim 13 further comprising:
applying a source line voltage to the second terminal of the resistive storage element of the first memory cell and to a second terminal of a resistive storage element of the second memory cell.

### Claim 16 (depends on 13)

The method of claim 13 further comprising:
during a write operation:
applying a write voltage to the first current electrodes of the first and second transistors in the first memory cell, and
enabling a word line coupled to the first memory cell.

### Claim 17 (depends on 13)

The method of claim 13 wherein the sense current is adjusted by
precharging a first capacitor to a reference voltage during a calibration phase; and
coupling a first terminal of the first capacitor to the first current electrode of the second transistor in the first memory cell during a sensing phase, wherein a second terminal of the first capacitor is coupled to a first input of an amplifier.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
precharging a second capacitor to a supply voltage during a calibration phase; and
coupling a first terminal of the second capacitor to the first current electrode of the first transistor in the second memory cell during a sensing phase, wherein a second terminal of the second capacitor is coupled to a second input of the amplifier.

### Claim 19 (depends on 13)

The method of claim 13 wherein the first resistive storage element is a non-volatile programmable resistor.

### Claim 20

An integrated circuit device comprising:
a memory device including:
a first memory cell having a first transistor, a second transistor, and a non-volatile programmable resistor;
a bit line coupled to a first current electrode of the first transistor during a read operation;
a sense amplifier including an input coupled to a first current electrode of the second transistor during the read operation;
a write voltage coupled to the first current electrode of the first and second transistors during a write operation;
a second current electrode of the first and second transistors coupled to a first terminal of the non-volatile programmable resistor;
a source line coupled to a second terminal of the non-volatile programmable resistor;
a word line coupled to a control electrode of the first and second transistors.