# US 9,520,167 B2 · Semiconductor memory device using delays to control column signals for different memory regions

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- Number: US 9,520,167 B2
- Document ID: US9520167B2
- Status: Granted
- Kind: B2
- Application number: 14/943,639
- Filed: 2015-11-17
- Published: 2016-03-10
- Granted: 2016-12-13
- Earliest claimed: 2012-08-28
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Heat-Bit Park
- Web page: https://patentgrep.com/patent/US9520167B2

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1087: {Data input latches}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 8/10: Decoders
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
- G11C 2207/229: Timing of a write operation
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

## Claims

### Claim 1

A semiconductor memory device comprising:
a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region through data is input/output, respectively; and
a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the plurality of delay times includes delay times in which a data transmission line, through which the data is input/output, has been modeled corresponding to arrangement locations of a plurality of unit memory regions.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the data transmission line includes a local input/output line.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2, wherein the first signal generation unit includes an RC delay for modeling the data transmission line.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein the first delay signal is delayed once as long as the selected delay time as compared with the first column control signal, and the second delay signal is delayed twice as long as the selected delay time as compared with the first column control signal.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the first column control signal includes a write enable signal for enabling a write driver, and the second column control signal includes a first column source signal used as a source signal when a column decoder generates a column selection signal for write.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein the selected delay time has a relatively large value among the plurality of delay times as the arrangement location of the unit memory region, through the data is input/output, is distant from the write driver.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1, wherein the first column control signal includes a second column source signal used as a source signal when a column decoder generates a column selection signal for read, and the second column control signal includes a read enable signal for enabling an input/output sense amplifier (IOSA).

### Claim 9 (depends on 8)

The semiconductor memory device of claim 8, wherein the selected delay time has a larger value among the plurality of delay times as the arrangement location of the unit memory region, through the data is input/output, become more distant from the input/output sense amplifier.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein the second signal generation unit includes an SR latch.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, wherein the first signal generation unit comprises:
a first replica delay section configured to delay the first column control signal by a delay time corresponding to arrangement locations of a plurality of unit memory regions to generate the first delay signal;
a second replica delay section configured to delay the first delay signal by the delay time to generate the second delay signal.

### Claim 12 (depends on 6)

The semiconductor memory device of claim 6, wherein the second signal generation unit comprises:
a first logic operation section configured to perform a first logic operation on the write enable signal and the first delay signal to generate a first set signal;
a second logic operation section configured to perform a second logic operation on the first delay signal and the second delay signal to generate a first reset signal; and
a third logic operation section configured to perform a third logic operation on the first set signal and the first reset signal to generate the second column source signal
wherein the first delay signal has a phase substantially equal to a phase of the write enable signal, and the second delay signal has a phase different from the phase of the write enable signal.

### Claim 13 (depends on 11)

The semiconductor memory device of claim 11, wherein the first replica delay section comprises:
a first modeling part configured to have a plurality of unit delay cells coupled in series, and to provide a plurality of delay paths in which different delay times have been modeled corresponding to the arrangement locations of the plurality of unit memory regions; and
a first selection part configured to select one of a plurality of delayed write enable signals, which are output through the plurality of delay paths, based on the selection signal, and to output the selected signal as the first delay signal.

### Claim 14 (depends on 8)

The semiconductor memory device of claim 8, wherein an activation time point of the first column source signal is determined in response to the first delay signal, and a deactivation time point of the first column source signal is determined in response to the second delay signal.