# US 9,520,166 B2 · Semiconductor memory device and operation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,166 B2 - Document ID: US9520166B2 - Status: Granted - Kind: B2 - Application number: 14/666,360 - Filed: 2015-03-24 - Published: 2015-07-09 - Granted: 2016-12-13 - Earliest claimed: 2012-08-03 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Shigeki Kobayashi; Takeshi Yamaguchi - Web page: https://patentgrep.com/patent/US9520166B2 ## CPC - G11C 13/004: {Reading or sensing circuits or methods} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0021: {Auxiliary circuits} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/0064: {Verifying circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 11/00: Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (G11C14/00 - G11C21/00 take precedence) - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C 2013/0057: {Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value} - G11C 2213/71: Three dimensional array - G11C 2213/72: Array wherein the access device being a diode - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line. ## Claims ### Claim 1 A semiconductor memory device, comprising: a memory cell array including, a plurality of first lines disposed above a substrate, a plurality of second lines disposed intersecting the first lines, and variable resistance elements disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively, such that a first potential difference is applied to a selected variable resistance element disposed at the intersection of the selected first line and the selected second line, the control circuit including a detection circuit configured to, during the setting operation, detect a transition of a resistance state of the selected variable resistance element using a reference voltage, and the control circuit being configured to, before the setting operation, execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line during the read operation. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to, when executing the setting operation on a plurality of the selected variable resistance elements, execute the read operation and the setting operation on each single one of the selected variable resistance elements. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to, before the setting operation on a plurality of the selected variable resistance elements, detect voltage values of a plurality of the selected second lines by a plurality of times of the read operation. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein a plurality of the memory cell arrays are stacked in a direction perpendicular to the substrate. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the variable resistance element changes from a high-resistance state to a low-resistance state by the first potential difference. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the third voltage and the fourth voltage are an identical voltage. ### Claim 7 A method of operating a semiconductor memory device, the semiconductor memory device comprising a memory cell array including a plurality of first lines disposed above a substrate, a plurality of second lines disposed intersecting the first lines, and variable resistance elements disposed at each of intersections of the first lines and the second lines and each configured having a variable resistance element, and the semiconductor memory device configured to execute a setting operation in which a first voltage is applied to a selected first line, a second voltage having a voltage value which is smaller than that of the first voltage is applied to a selected second line, and a third voltage and a fourth voltage are applied to a non-selected first line and a non-selected second line, respectively, such that a first potential difference is applied to a selected variable resistance element disposed at the intersection of the selected first line and the selected second line, the method comprising: before the setting operation, executing a read operation in which the third voltage is applied to the selected first line and the non-selected first line, the second voltage is applied to the selected second line, and the fourth voltage is applied to the non-selected second line, and setting a reference voltage based on a voltage value of the selected second line during the read operation; and during the setting operation, detecting a transition of a resistance state of the selected variable resistance element using the reference voltage. ### Claim 8 (depends on 7) The method of operating a semiconductor memory device according to claim 7, wherein when the setting operation is executed on a plurality of the selected variable resistance elements, the read operation and the setting operation are executed on each single one of the selected variable resistance elements. ### Claim 9 (depends on 7) The method of operating a semiconductor memory device according to claim 7, wherein before the setting operation on a plurality of the selected variable resistance elements, voltage values of a plurality of the selected second lines are detected by a plurality of times of the read operation. ### Claim 10 (depends on 7) The method of operating a semiconductor memory device according to claim 7, wherein the variable resistance element changes from a high-resistance state to a low-resistance state by the first potential difference. ### Claim 11 (depends on 7) The method of operating a semiconductor memory device according to claim 7, wherein the third voltage and the fourth voltage are an identical voltage.