# US 9,520,165 B1 · High-speed pseudo-dual-port memory with separate precharge controls

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- Number: US 9,520,165 B1
- Document ID: US9520165B1
- Status: Granted
- Kind: B1
- Application number: 14/745,216
- Filed: 2015-06-19
- Published: 2016-12-22
- Granted: 2016-12-13
- Earliest claimed: 2015-06-19
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Nishith Nitin Desai; Tony Chung Yiu Kwok; Changho Jung
- Web page: https://patentgrep.com/patent/US9520165B1

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/08: Control thereof
- G11C 11/419: Read-write [R-W] circuits
- G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.

## Claims

### Claim 1

A pseudo-dual-port (PDP) memory, comprising:
a pair of bit lines;
a bit line precharge circuit configured to precharge the pair of bit lines responsive to an assertion of a bit line precharge signal;
a read multiplexer configured to selectively couple the pair of bit lines to a pair of input nodes of a sense amplifier responsive to an assertion of a read multiplexer signal;
a sense amplifier precharge circuit for precharging the pair of input nodes of the sense amplifier responsive to an assertion of a sense amplifier precharge signal; and
a control signal generator configured to assert the bit line precharge signal responsive to a self-timed falling edge of a first memory clock that occurs while a sense enable signal is asserted during a read operation in a first portion of a system clock cycle and to assert the sense amplifier precharge signal responsive to a falling edge of the sense enable signal to precharge the pair of input nodes for the sense amplifier prior to a write operation in a second portion of the system clock cycle.

### Claim 2 (depends on 1)

The PDP memory of claim 1, wherein the control signal generator is further configured to de-assert the bit line precharge signal responsive to a rising edge of the first memory clock.

### Claim 3 (depends on 2)

The PDP memory of claim 2, wherein the first memory clock comprises a bank memory clock having a rising edge responsive to a rising edge of a system clock and the self-timed falling edge.

### Claim 4 (depends on 2)

The PDP memory of claim 2, wherein the control signal generator comprises a serial chain of inverters configured to delay the first memory clock to produce the bit line precharge signal.

### Claim 5 (depends on 4)

The PDP memory of claim 4, wherein the serial chain of inverters comprises a serial pair of inverters.

### Claim 6 (depends on 1)

The PDP memory of claim 1, wherein the control signal generator is further configured to de-assert the sense amplifier precharge signal responsive to a rising edge of a second memory clock.

### Claim 7 (depends on 6)

The PDP memory of claim 6, wherein the second memory clock comprises a read clock.

### Claim 8 (depends on 7)

The PDP memory of claim 7, wherein the control signal generator comprises:
a serial chain of inverters configured to delay the sense enable signal to produce a delayed sense enable signal, and
a logic gate configured to process the delayed sense enable signal and the read clock to produce the sense amplifier precharge signal.

### Claim 9 (depends on 8)

The PDP memory of claim 8, wherein the logic gate comprises a NOR gate, and wherein the control signal generator further comprises an inverter to invert an output signal from the NOR gate to produce the sense amplifier precharge signal.

### Claim 10 (depends on 1)

The PDP memory of claim 1, wherein the bit line precharge circuit comprises a first PMOS transistor having its source tied to a power supply node and its drain tied to a true one of the bit lines, and wherein the bit line precharge circuit further comprises a second PMOS transistor having its source tied to the power supply node and its drain tied to a remaining complement one of the bit lines, wherein the first PMOS transistor and the second PMOS transistor are each configured to have their gates driven by the bit line precharge signal.

### Claim 11 (depends on 1)

The PDP memory of claim 1, wherein the sense amplifier precharge circuit comprises a first PMOS transistor having its source tied to a power supply node and its drain tied to a first one of the input nodes, and wherein the bit line precharge circuit further comprises a second PMOS transistor having its source tied to the power supply node and its drain tied to a remaining second one of the input nodes, wherein the first PMOS transistor and the second PMOS transistor are each configured to have their gates driven by the sense amplifier precharge signal.

### Claim 12 (depends on 1)

The PDP memory of claim 1, wherein the sense amplifier comprises a pair of cross-coupled inverters.

### Claim 13 (depends on 12)

The PDP memory of claim 12, wherein the sense amplifier further comprises a current source transistor coupled between ground and a ground node for the pair of cross-coupled inverters, and wherein the current source transistor is configured to have its gate driven by the sense enable signal.

### Claim 14 (depends on 13)

The PDP memory of claim 13, wherein the current source transistor comprises an NMOS transistor.

### Claim 15

A method, comprising:
coupling a pair of bit lines to a corresponding pair of input nodes for a sense amplifier during a read operation in a first portion of a system clock cycle for a pseudo-dual-port memory to develop a voltage difference across the input nodes;
asserting a sense enable signal for a sense amplifier assertion period during the read operation to cause the sense amplifier to sense the voltage difference;
during the sense amplifier assertion period in the read operation, precharging the bit lines while isolating the pair of bit lines from the pair of input nodes;
after a completion of the sense amplifier enable assertion period, precharging the pair of input nodes while isolating the pair of bit lines from the pair of input nodes for a write operation in a second portion of the system clock cycle for the pseudo-dual-port memory.

### Claim 16 (depends on 15)

The method of claim 15, wherein precharging the bit lines comprises precharging the bit lines responsive to a falling edge of a memory clock.

### Claim 17 (depends on 16)

The method of claim 16, wherein the memory clock comprises a bank clock.

### Claim 18 (depends on 15)

The method of claim 15, wherein precharging the pair of input nodes is responsive to a falling edge of the sense enable signal.

### Claim 19

A pseudo-dual-port (PDP) memory, comprising:
a pair of bit lines;
a bit line precharge circuit configured to precharge the pair of bit lines responsive to an assertion of a bit line precharge signal;
a read multiplexer configured to selectively couple the pair of bit lines to a corresponding pair of input nodes of a sense amplifier responsive to an assertion of a read multiplexer signal;
a sense amplifier precharge circuit for precharging the pair of input nodes of the sense amplifier responsive to an assertion of a sense amplifier precharge signal;
first means for asserting the bit line precharge signal responsive to a delayed version of a falling edge of a memory clock for a read operation during a first portion of a system clock cycle and for de-asserting the bit line precharge signal responsive to a delayed version of a rising edge of the memory clock; and
second means for asserting the sense amplifier precharge signal responsive to a delayed version of a falling edge for a sense enable signal to precharge the pair of input nodes for the sense amplifier prior to a write operation in a second portion of the system clock cycle.

### Claim 20 (depends on 19)

The PDP memory of claim 19, further comprising a plurality of SRAM bit cells; and a corresponding plurality of word lines.