# US 9,520,164 B1 · ZQ calibration circuit and semiconductor device including the same

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- Number: US 9,520,164 B1
- Document ID: US9520164B1
- Status: Granted
- Kind: B1
- Application number: 14/947,955
- Filed: 2015-11-20
- Granted: 2016-12-13
- Earliest claimed: 2015-09-04
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Kensuke Yamamoto; Kosuke Yanagidaira; Shouichi Ozaki
- Web page: https://patentgrep.com/patent/US9520164B1

## CPC

- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- H03K 19/17764: for reliability
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

According to one embodiment, a ZQ calibration circuit comprises a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.

## Claims

### Claim 1

A ZQ calibration circuit, comprising:
a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.

### Claim 2 (depends on 1)

The ZQ calibration circuit of claim 1, wherein the replica buffer controller inputs a stress application signal allowing the electric stress to be applied, to the replica buffer controller in response to a data signal or a data strobe signal output from the output buffer circuit.

### Claim 3 (depends on 2)

The ZQ calibration circuit of claim 2, wherein the replica buffer controller adjusts a frequency or a duty ratio of the stress application signal.

### Claim 4 (depends on 1)

The ZQ calibration circuit of claim 1, further comprising a first adjustment circuit configured to adjust a power supply voltage for the replica buffer circuit.

### Claim 5 (depends on 1)

The ZQ calibration circuit of claim 1, further comprising a second adjustment circuit configured to adjust a load-carrying capacity of the replica buffer circuit.

### Claim 6 (depends on 1)

The ZQ calibration circuit of claim 1, wherein the replica buffer controller inputs a stress application signal allowing the electric stress to be applied to the replica buffer circuit in response to a read command.

### Claim 7 (depends on 6)

The ZQ calibration circuit of claim 6, wherein the replica buffer controller coordinates a timing to input the stress application signal with other semiconductor chips operating in parallel in an identical package.

### Claim 8

A ZQ calibration circuit, comprising:
a plurality of replica buffer circuits having a circuit configuration substantially identical to a circuit configuration of an output buffer circuit and to which different electric stresses are pre-applied; and
a selection circuit configured to select one of the plurality of replica buffer circuits according to a usage status of the output buffer circuit.

### Claim 9 (depends on 8)

The ZQ calibration circuit of claim 8, wherein the selection circuit reads information including the usage status and a selection target associated with each other and selects one of the plurality of replica buffer circuits based on the information.

### Claim 10

A semiconductor device, comprising:
a ZQ calibration circuit, wherein
the ZQ calibration circuit comprises a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the replica buffer controller inputs a stress application signal allowing the electric stress to be applied to the replica buffer controller in response to a data signal or a data strobe signal output from the output buffer circuit.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the replica buffer controller adjusts a frequency or a duty ratio of the stress application signal.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising a first adjustment circuit configured to adjust a power supply voltage for the replica buffer circuit.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, further comprising a second adjustment circuit configured to adjust a load-carrying capacity of the replica buffer circuit.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the replica buffer controller inputs a stress application signal allowing the electric stress to be applied to the replica buffer circuit in response to a read command.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the replica buffer controller coordinates a timing to input the stress application signal with other semiconductor chips operating in parallel in an identical package.